Abstract: A p-type polycrystalline silicon layer (45) serving as the base electrode of an npn transistor and a p-type polycrystalline silicon layer (50) serving as the emitter electrode of a pnp transistor are simultaneously formed by forming a p-type polycrystalline silicon on the entire surface and patterning the same. Similarly, an n-type polycrystalline silicon layer (46) serving as the emitter electrode of the npn transistor and an n-type polycrystalline silicon layer (49) serving as the base electrode of the pnp transistor are simultaneously formed by forming an n-type polycrystalline silicon on the entire surface and patterning the same. Thus, electrodes can be formed without selective impurity implantation and the mask alignment therefor.

Abstract: A semiconductor device having a thin package profile is leadless, thereby minimizing necessary mounting space on a substrate. In one form, a semiconductor device has a semiconductor die electrically coupled to a plurality of conductive leads. Each lead has a first portion, a second portion, and an intermediate portion which separates the first and second portions. A package body encapsulates the semiconductor die and the first and intermediate portions of the leads. The second portions of the leads are exposed on the bottom surface of the package body and are used to electrically access the semiconductor die.

Abstract: A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.

Abstract: A reaction barrier is formed at an interface region between adjacent layers of a multilayer composite integrated circuit by implanting one or more active ionic species at energies effective to place the ionic species at or near the interface. A further step may include annealing the structure formed above to promote efficacy of the reaction barrier.

Abstract: In a n-channel MOS transistor of LDD structure with sidewall spacers, a p-type diffusion layer is formed to be on the surface of a n.sup.- drain layer just underneath the sidewall spacer and to be separated from the channel region. The low impurity concentration drain layer therefore becomes separated from the sidewall spacer, and thus degradation incident to LDD due to injection of hot carriers into the sidewall spacer can be prevented.

Abstract: Herein disclosed is a bipolar-CMOS semiconductor circuit having a semiconductor substrate, an N.sup.- epitaxial layer formed on the semiconductor substrate, an N well formed in the N.sup.- epitaxial layer, a P well formed in the N.sup.- epitaxial layer, a power supply terminal to which the positive potential is to be supplied, a ground potential terminal, an input terminal, an output terminal, an NPN bipolar transistor formed in the N.sup.- epitaxial layer, the NPN bipolar transistor having the N.sup.- epitaxial layer as the collector thereof and having an emitter connected to the output terminal, a P-channel type MOS transistor formed in the N well and being connected between the power supply terminal and the base of the NPN bipolar transistor, the gate of the P-channel type MOS transistor being connected to the input terminal, and both the N well for the P-channel type MOS transistor and the N.sup.

Abstract: An impingement cooled compliant heat sink (CHS) is employed to extract heat from an array of computer chips in an electric module. A variety of embodiments and variations are provided. The most basic implementation is a metal sheet that is brought into contact with chips on a multi-chip module, and acts as a spreader plate for jet impingement immersion cooling with fluorocarbon, liquid nitrogen, or other dielectric liquids. This can increase cooling at a given flow rate by increasing the area for heat transfer. Slots and/or holes in teh sheet located between the chip sites serve to: (1) create flexible joints in the sheet between the chips to permit conformity to neighboring chip sites, (2) allow for clearance of decoupling capacitors and other structures on the substrate between the chips, and (3) permit the dielectric coolant to flow through the plate so that there will be no pressure difference across the CHS.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type. An insulative film and metal films are sequentially formed on the main top surface of the semiconductor substrate. Impurity diffusion layers of a second conductivity type are selectively formed on the main top surface of the semiconductor substrate. The semiconductor device further includes metal compound layers consisting of constituting elements of the semiconductor substrate and a metal element. The metal compound layers are formed in the impurity diffusion layers in such a manner that they do not contact the insulative film, and the metal compound layers on the main back surface side of the semiconductor substrate have faces formed in parallel to the top surface of the semiconductor substrate.

Abstract: An integrated circuit chip package having a substrate containing integrated circuit chips thereon; signal input/out connections for the chips located at edges of a substrate; and conductive power planes are separated from the signal input/output connections and are removably connected to the substrate.

Abstract: A bipolar transistor is formed from epitaxial cubic boron nitride grown on a silicon substrate which is a three to two commensurate layer deposited by pulsed laser evaporation techniques. The thin film, cubic boron nitride bipolar transistor is in epitaxial registry with an underlying single crystal silicon substrate. The bipolar transistor is particularly suitable for high temperature applications.

Abstract: A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44). Source conductor (36) and drain conductor (38) are disposed to create inversion regions, and a second conductivity type opposite said first conductivity type, in the underlying source inversion region (40) and drain inversion region (42) of semiconductor layer (12) upon application of voltage. The transistor has a gate (54) insulatively overlying the channel region (44) to control the conductivity thereof.

Abstract: A method of forming an insulated-gate field-effect transistor, and the transistor formed thereby, is described. According to a first embodiment, an inverted-T gate structure is formed by the deposition of a polycrystalline silicon layer, followed by the deposition of a metal silicide layer thereover. The metal silicide layer is etched with etchant which does not significantly etch polysilicon, to define the upper portion of the gate electrode. The reachthrough lightly-doped source/drain extensions are then implanted through the polysilicon layer, using the upper gate electrode portion as a mask. Sidewall spacers are formed on the sides of the upper portion of the gate electrode, and the polysilicon etched using the spacers as a mask, to define the inverted-T gate structure.

Abstract: In a multi-layered integrated memory circuit, a method for using sacrificial layers and insulating "sticks" is disclosed to provide a contact between two layers, where the contact does not short to an intervening layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.

Abstract: Superconducting electrodes are formed on a semiconductor which serves as a channel. A control electrode is disposed through an insulator film or a p-n junction on the side of the semiconductor which is opposite to the semiconductor side on which the superconducting electrode is formed. A superconducting current which flows between the superconducting electrodes across the semiconductor is controlled by an electric signal which is applied to the control electrode, thereby enhancing the current gain.

Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.

Abstract: An injection molded aluminum nitride heatsink forms the substrate of an integral heatsink semiconductor package in which a semiconductor chip is attached directly to the integrated heatsink forming an intimate thermal relationship between the heat generating source and the heat dissipating means. In a first embodiment, a planar surface of the heatsink component provides the substrate for the attachment of a semiconductor chip and a multilayer housing formed from a plurality of layers of dielectric glass ceramic lamina and conductive circuit layers. The multilayer housing is formed on top of the heatsink substrate creating a recessed cavity in which the semiconductor die sits and is attached directly to the heatsink. The semiconductor chip is attached to the circuit layers of the housing through any of the known electrical connection methods, such as wirebonding or tab tape. A cover plate is mounted over the cavity.

Abstract: A tape carrier used for assemblage of integrated circuit chips based on a TAB system, comprises a plurality of square frames, each including a substantially square opening for defining a position of an integrated circuit chip to be bonded to the frame, the square opening being formed within a mold area of the frame on which, when the integrated circuit chip mounted at the square opening and bonded to the frame is resin-molded, the resin-molded integrated circuit chip extends. At least two substantially rectangular first openings are formed within the mold area at a space between the square opening and an outer periphery of the mold area. A plurality of lead groups, extend from an inside of the square opening to positions adjacent to a periphery of the frame by crossing one of the first openings.

Abstract: This invention relates to a thin film semiconductor device and a method for fabricating it, and more particularly a thin film semiconductor device suitably applicable to a display device in an active matrix system and a method for fabricating it. In this invention, the structure of a thin film semiconductor device for improving the characteristic thereof and particularly the structure relative to the dominant orientation of a poly-Si film as an active layer of a thin film transistor (TFT) is disclosed. A method for fabricating a thin film semiconductor device which is capable of forming a poly-Si film at a relatively low process temperature is disclosed. Further, a display device in an active matrix system which provided high performance and high image quality is disclosed. The poly-Si film having a dominant orientation of (111) is formed by forming a poly-Si film on the semiconductor substrate at a temperature up to 570.degree. C. and annealing the substrate at a temperature up to 640.degree. C.

Abstract: A dielectric isolation substrate includes island-like regions made of a single crystal of semiconductor material and a supporting layer for supporting the island-like regions. The support layer is formed by first and second electrodes made of a conductive material and a dielectric film interposed therebetween to constitute a capacitor structure. The first electrode layer has a plurality of island-like regions on a principal surface side thereof remote from the dielectric film. The first electrode layer may be formed as one region for forming one capacitor or isolated two or more regions for forming two or more capacitors.

Abstract: A heterojunction field-effect transistor includes a first electron transit channel formation semiconductor layer formed on a substrate and consisting of a compound semiconductor, a first electron supply semiconductor layer formed on the first electron transit channel formation semiconductor layer and consisting of a compound semiconductor, a gate electrode, a source electrode, and a drain electrode formed on the first electron supply semiconductor layer, and a second electron transit channel formation semiconductor layer formed between the substrate and the first electron transit channel formation semiconductor layer.