Abstract: A method includes forming an n-FET device and a p-FET device on a substrate, each of the n-FET device and the p-FET device include a metal gate stack consisting of a titanium-aluminum carbide (TiAlC) layer above and in direct contact with a titanium nitride (TiN) cap, and removing, from the p-FET device, the TiAlC layer selective to the TiN cap. The removal of the TiAlC layer includes using a selective TiAlC to TiN wet etch chemistry solution with a substantially high TiAlC to TiN etch ratio such that the TiN cap remains in the p-FET device.

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Abstract: A method of manufacturing an EL display device having a panel part is such that a constituent element of the panel part is formed through film formation in a vacuum atmosphere. After the constituent element of the panel part has been formed on a substrate in the vacuum atmosphere, the post-film-formation substrate is placed on standby during transporting the substrate from a place in the vacuum atmosphere to a place in an atmospheric-pressure atmosphere. The placing the substrate on standby includes a first intake period and a second intake period. During the first intake period, an intake gas is gradually introduced to change the atmosphere, from the first vacuum atmosphere to the second vacuum atmosphere that exhibits a lower degree of vacuum than that of the first vacuum atmosphere. During the second intake period, the intake gas is introduced to change the atmosphere, from the second vacuum atmosphere to the atmospheric-pressure atmosphere.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

Abstract: In at least one embodiment, the semiconductor layer sequence (1) is provided for an optoelectronic semiconductor chip (10). The semiconductor layer sequence (1) contains at least three quantum wells (2) which are arranged to generate electromagnetic radiation. Furthermore, the semiconductor layer sequence (1) includes a plurality of barrier layers (3), of which at least one barrier layer is arranged between two adjacent quantum wells (2) in each case. The quantum wells (2) have a first average indium content and the barrier layers (3) have a second, smaller, average indium content. A second average lattice constant of the barrier layers (3) is thereby smaller than a first average lattice constant of the quantum wells (2).

Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.

Abstract: A MEMS device wherein a die of semiconductor material has a first face and a second face. A membrane is formed in or on the die and faces the first surface. A cap is fixed to the first face of the first die and is spaced apart from the membrane by a space. The die is fixed, on its second face, to an ASIC, which integrates a circuit for processing the signals generated by the die. The ASIC is in turn fixed on a support. A packaging region coats the die, the cap, and the ASIC and seals them from the outside environment. A fluidic path is formed through the support, the ASIC, and the first die, and connects the membrane and the first face of the die with the outside, without requiring holes in the cap.

Abstract: In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Abstract: A back-contact solar cell module and a process for making such a solar cell module are provided. The module includes a porous wire mounting layer with a plurality of elongated electrically conductive wires mounted thereon. A polymeric encapsulant layer is provided between a rear surface of solar cells of the module and the porous wire mounting layer and is melted to adhere to the solar cells and penetrate the porous wire mounting layer. Back electrical contacts on the solar cells are electrically connected to the electrically conductive wires through the porous wire mounting layer.

Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.

Abstract: An organic light emitting display device having a display substrate; a display element layer formed on the display substrate and including a plurality of pixels, a thin film encapsulation layer which covers and protects the display substrate and the display element layer; a function film disposed on the thin film encapsulation layer, a first adhesive layer disposed between the thin film encapsulation layer and the functional film, a window attached onto the functional film which protects the display element layer, and a second adhesive layer disposed between the functional film and the window, in which the first adhesive layer and the second adhesive are formed by deposition, a surface processing is performed, and facing surfaces are adhered with each other.

Abstract: An image sensor includes a semiconductor substrate, a storage node region in the semiconductor substrate, an insulating portion on the semiconductor substrate, a via contact extending through the insulating portion, a photo-electric converter in the semiconductor substrate and spaced apart from the storage node region, an organic photo-electric layer on the insulating portion, and a buffer interposed between and electrically connecting the via contact and the storage node region.

Abstract: A thin film transistor array panel and a display device including the same are disclosed. In one aspect, the thin film transistor array panel includes a plurality of dots located in a display area, each of the plurality of dots including a plurality of pixels, and a plurality of data lines applying data voltages to the plurality of pixels. The thin film transistor array panel also includes a plurality of first dummy data lines located in a first peripheral area of a peripheral area around the display area, the plurality of first dummy data lines are adjacent to a first edge of the display area. The thin film transistor array panel further includes plurality of first data lines applying data voltages to the pixels included in a first dot adjacent to the first edge and are respectively connected to the plurality of first dummy data lines.

Abstract: There is provided a light emitting device including a light emitting element, a covering member for covering a side surface of the light emitting element, and a light-transmissive member disposed on upper surfaces in a light emitting direction of the light emitting element and the covering member and having an end face on substantially the same plane as an end face of the covering member, wherein the covering member has a recess portion or a convex portion on the upper surface, a light emitting surface of the light emitting element and an upper surface other than the recess portion or the convex portion of the covering member are arranged on substantially the same plane, and the light-transmissive member is provided in contact with the recess portion or the convex portion.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: A normally-off-type HFET includes: an undoped AlwGa1-wN layer of t1 thickness, an undoped AlxGa1-xN layer of t2 thickness and an undoped GaN channel layer of tch thickness that are sequentially stacked; a source electrode and a drain electrode separated from each other and electrically connected to the channel layer; an undoped AlyGa1-yN layer of t3 thickness formed between the source electrode and the drain electrode on the channel layer; an AlzGa1-zN layer of t4 thickness formed in a shape of a mesa on a partial area of the AlyGa1-yN layer between the source electrode and the drain electrode; and a Schottky barrier type gate electrode formed on the AlzGa1-zN layer, in which conditions of y>x>w>z, t1>t4>t3 and 2wtch/(x?w)>t2>1 nm are satisfied.

Abstract: A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the die pad of the lead frame, and bonding wires for electrically interconnecting the lead of the lead frame and the semiconductor element. The lead frame, the semiconductor element, and the bonding wires are sealed with a sealing resin section. The sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region. Thickness of the central region is greater than that of the marginal region.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Abstract: A magnetic field effect transistor is presented. A magnetic field effect transistor comprises a current control part and a magnetic field applying part. A current control part comprises multiple electrodes and a current flowing material region located between multiple electrodes and in which the amount of current flowing between the electrodes is changed, and a magnetic field applying part applying a magnetic field generating from a magnetization state, which changes according to external input, of a pre-set material. By controlling current by using magnetic fields, high speed operation is possible as charging time is not required, and calculation results may be stored without external power supply because magnetic field is supplied by altering magnetization state of a material according to external input.

Abstract: A method of forming a semiconductor device package includes bonding a front surface of a first substrate to a second substrate, and thinning a back surface of the first substrate. The method includes depositing and patterning a dielectric layer on the thinned back surface of the first substrate, and etching the first substrate after the depositing and the patterning of the dielectric layer are performed to form a through silicon via to enable electrical connection with a first level metal of the first substrate. The method includes depositing an isolation layer to line the through silicon via is formed, and etching the isolation layer at the bottom of the through silicon via. The method includes depositing a conductive layer to line the through silicon via after the isolation layer at the bottom of the through silicon via is etched, and deposited a copper film over the conductive layer.