Abstract: In one embodiment, a semiconductor package comprising a metal base coupled to one or more pins, a semiconductor body having a top side and a bottom side, the top side comprising an integrated circuit and one or more metal surfaces for coupling the integrated circuit to the one more pins with one or more bonding wires, the bottom side non-positively coupled to the metal base, a disk having a top area and a base area, the base area coupled to the top side of the semiconductor body and at least partially covering the integrated circuit, the disk being electrically insulated from the semiconductor body, and a plastic compound completely enclosing the one or more bonding wires, and at least partially enclosing the top side of the integrated circuit, the top area of the disk, and the one or more pins.

Abstract: A display includes: a first light-emitting device disposed in a first region on a substrate and including a transfer organic layer; a second light-emitting device disposed in a second region adjacent to the first region on the substrate and not including a transfer organic layer; and a level difference provided between the first region and the second region, and being large enough to inhibit transfer of the transfer organic layer to the second region when the transfer organic layer is formed in the first region.

Abstract: A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components.

Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).

Abstract: A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.

Abstract: An apparatus comprising a first substrate and a second substrate. The first substrate has disposed thereon a first feature. The second substrate has disposed thereon a second feature. The first feature is configured to interlock with the second feature such that the first substrate and the second substrate are aligned by the first and the second features within a predefined accuracy.

Abstract: An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

Abstract: The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 ?m, preferably from 5-40 ?m, like 20 ?m.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

Abstract: A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.

Abstract: A method of forming a light-emitting device (LED) package component includes providing a substrate; forming an LED on the substrate; and lifting the LED off the substrate. A carrier wafer is provided, which includes a through-substrate via (TSV) configured to electrically connecting features on opposite sides of the carrier wafer. The LED is bonded onto the carrier wafer, with the LED electrically connected to the TSV.

Abstract: A flip chip semiconductor packaging device and method that incorporates in situ formation of cavities underneath selected portions of a die during a flip chip die bonding process. A method of flip chip semiconductor component packaging includes providing a die having a first surface, forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die, bonding the die to a substrate in a flip chip configuration, and flowing molding compound over the die and over at least a portion of the substrate. Bonding the die to the substrate includes causing contact between the barrier and the substrate such that flow of the molding compound is blocked by the barrier to provide a cavity between the die and the substrate, the cavity being proximate the designated location on the first surface of the die.

Abstract: A light-emitting diode includes a substrate, a first semiconductor layer above the substrate, an active layer above the first semiconductor layer, a second semiconductor layer above the active layer, wherein the active layer is between the first semiconductor layer and the second semiconductor layer a trench penetrating through the second semiconductor layer and the active layer to expose the first semiconductor layer a first electrode disposed at a bottom of the trench, wherein the first electrode includes at least one first finger, an insulating layer covering the first electrode, and a second electrode including at least one second finger on the insulating layer, wherein the second finger overlaps with the first finger and the second finger has a width smaller than that of the trench.

Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Abstract: A high power density photo-electronic and photo-voltaic material comprising a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein encapsulated inside a multi-wall carbon nanotube or nanotube array. The array can be on an electrode. The photosynthetic reaction center protein can be immobilized on the electrode surface and the protein molecules can have the same orientation. A method of making a high power density photo-electronic and photo-voltaic material comprising the steps of immobilizing a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein inside a carbon nanotube, wherein the immobilizing is by passive diffusion, wherein the immobilizing can include using an organic linker.

Abstract: A contact pad for an electronic device integrated in a semiconductor material chip is formed from a succession of protruding elements. Each protruding element extends transversally to a main surface of the chip and has a rounded terminal portion. Adjacent pairs protruding elements define an opening which is partially filled with a first conductive material to form a contact structure that is in electrical contact with an integrated electronic device formed in the chip. A layer of a second conductive material is deposited to cover said protruding elements and the contact structures so as to form the contact pad.

Abstract: Silicon wafers having a resistivity >6 ?cm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant.

Abstract: A package substrate includes: a first conductive layer having plural first terminal pattern portions connected to a semiconductor part loaded on a first principal surface through plural first external connection conductors, which is formed on the first principal surface; a second conductive layer having plural second terminal patterns connected to a system substrate mounted on a second principal surface opposite to the first principal surface through a second external connection conductor, which is formed on the second principal surface; an intermediate conductive layer formed between the first conductive layer and the second conductive layer; interlayer insulating layers formed between the first conductive layer and the intermediate conductive layer as well as between the second conductive layer and the intermediate conductive layer; and plural interlayer connection conductors stacked for connecting between the first conductive layer and the second conductive layer so as to pierce through the interlayer insu

Abstract: A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias.

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.