Patents Examined by Edward Wojciechowicz
  • Storage nodes, magnetic memory devices, and methods of manufacturing the same
    Patent number: 8803266
    Abstract: A storage node of a magnetic memory device includes: a lower magnetic layer, a tunnel barrier layer formed on the lower magnetic layer, and a free magnetic layer formed on the tunnel barrier. The free magnetic layer has a magnetization direction that is switchable in response to a spin current. The free magnetic layer has a cap structure surrounding at least one material layer on which the free magnetic layer is formed.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-seok Kim, U-In Chung, Jai-kwang Shin, Kee-won Kim, Sung-chul Lee, Ung-hwan Pi
  • Floating body memory cell apparatus and methods
    Patent number: 8803213
    Abstract: Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Paul Grisham
  • Package structures and methods for forming the same
    Patent number: 8803323
    Abstract: A device includes a first package component and the second package component. The first package component includes a first plurality of connectors at a top surface of the first package component, and a second plurality of connectors at the top surface. The second package component is over and bonded to the first plurality of connectors, wherein the second plurality of connectors is not bonded to the second package component. A solder resist is on the top surface of the first package component. A trench is disposed in the solder resist, wherein a portion of the trench spaces the second plurality of connectors apart from the first plurality of connectors.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jiun Yi Wu, Tsung-Ding Wang
  • Semiconductor device and manufacturing method thereof
    Patent number: 8796780
    Abstract: Provided is a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively. The semiconductor device according to the one embodiment of the present invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first and second conductivity type MOSFETs are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control a work function thereof.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Yukio Nishida, Jiro Yugami
  • Creating anisotropically diffused junctions in field effect transistor devices
    Patent number: 8796771
    Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Jeffrey B. Johnson, Qingqing Liang, Edward P. Maciejewski
  • Light-emitting device and electronic apparatus
    Patent number: 8785948
    Abstract: A light-emitting device includes a drive transistor that controls a current to be supplied to a light-emitting element from a power supply line, an element continuity portion that electrically connects the drive transistor with the light-emitting element, an initializing transistor that is turned ON to diode-connect the drive transistor, and a connecting portion that electrically connects the drive transistor with the initializing transistor. The power supply line includes a first portion extending in a predetermined direction. The element continuity portion and the connecting portion are formed from the same layer as that of the power supply line and are located on one side along the width of the first portion across the drive transistor.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: July 22, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takehiko Kubota, Eiji Kanda, Ryoichi Nozawa
  • Integrated circuit chip protected against laser attacks
    Patent number: 8779552
    Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 ?m from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • TFT substrate and method for producing TFT substrate
    Patent number: 8778722
    Abstract: An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate comprises: a substrate; a first oxide layer formed above the substrate; a second oxide layer formed above the first oxide layer with a channel part interposed therebetween; gate insulating film formed above the substrate, the first oxide layer and the second oxide layer; a gate electrode and a gate wire formed above the gate insulating film.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: July 15, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Kazuyoshi Inoue, Koki Yano, Tokie Tanaka
  • Offset of contact opening for copper pillars in flip chip packages
    Patent number: 8772943
    Abstract: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 8, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Xueren Zhang, Kim-Yong Goh
  • Trench Schottky barrier diode and manufacturing method thereof
    Patent number: 8772900
    Abstract: The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer.
    Type: Grant
    Filed: July 8, 2012
    Date of Patent: July 8, 2014
    Assignee: Richteck Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Directionally etched nanowire field effect transistors
    Patent number: 8772755
    Abstract: A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Light-emitting device and electronic apparatus
    Patent number: 8772789
    Abstract: A light-emitting device includes a drive transistor that controls a current to be supplied to a light-emitting element from a power supply line, an electrical continuity portion that electrically connects the drive transistor with the light-emitting element, an initializing transistor that is turned ON to diode-connect the drive transistor, and a connecting portion that electrically connects the drive transistor with the initializing transistor. The power supply line including a first portion extending in a first direction and a second portion extending in a second direction that crosses the first direction. The connecting portion being positioned in an area between the first and second power supply lines in plan view.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: July 8, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takehiko Kubota, Eiji Kanda, Ryoichi Nozawa
  • Light emitting diode array and method for manufacturing the same
    Patent number: 8759121
    Abstract: An LED array includes a substrate and a plurality of LEDs formed on the substrate. The LEDs are electrically connected with each other. Each of the LEDs includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on the substrate in sequence. The connecting layer is etchable by alkaline solution. A bottom surface of the n-type GaN layer which connects the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity. A method for manufacturing the LED array is also provided.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: June 24, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Tzu-Chien Hung, Chia-Hui Shen
  • Package with multiple dies
    Patent number: 8754509
    Abstract: A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: June 17, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: David Grey
  • Stretchable form of single crystal silicon for high performance electronics on rubber substrates
    Patent number: 8754396
    Abstract: The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: June 17, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Dahl-Young Khang, Yugang Sun, Etienne Menard
  • Semiconductor device and manufacturing method thereof
    Patent number: 8749058
    Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Hideaki Tsuchiya, Yukio Miura, Tomoyuki Nakamura, Koichi Ohto, Chikako Ohto, Shinji Yokogawa
  • Ultraviolet light emitting device incorporating optically absorbing layers
    Patent number: 8748919
    Abstract: A light emitting device includes a p-side, an n-side, and an active layer between the p-side and the n-side. The p-side includes a p-side contact, an electron blocking layer, a p-side separate confinement heterostructure (p-SCH), and a p-cladding/current spreading region disposed between the p-SCH and the p-side contact. The n-side includes an n-side contact, and an n-side separate confinement heterostructure (n-SCH). The active layer is configured to emit light in a wavelength range, wherein the p-side and the n-side have asymmetrical optical transmission properties with respect to the wavelength range emitted by the active layer.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: June 10, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Christopher L. Chua
  • Semiconductor device and method of manufacturing the same
    Patent number: 8748282
    Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Kubota, Nobutaka Nagai, Satoshi Kura
  • Light-emitting diode with embedded elements
    Patent number: 8742441
    Abstract: A light-emitting diode (LED) device is provided. The LED device has a substrate and an LED structure overlying the substrate. Embedded elements are embedded within one or more layers of the LED structure. In an embodiment, the embedded elements include a dielectric material extending through the LED structure such that the embedded elements are surrounded by the LED structure. In another embodiment, the embedded elements only extend through an upper layer of the LED structure, or alternatively, partially through the upper layer of the LED structure. Another conductive layer may be formed over the upper layer of the LED structure and the embedded elements.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: June 3, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Ding-Yuan Chen, Wen-Chih Chiou, Chen-Hua Yu
  • Method for integrated circuit design and manufacture using diagonal minimum-width patterns
    Patent number: 8745555
    Abstract: Methods for designing and manufacturing an integrated circuit are disclosed, in which the physical design process for a standard cell or cells utilizes a preferred diagonal direction for minimum-width patterns on at least one layer, where the standard cell or cells are used in the layout of an integrated circuit. The methods also include forming the patterns on a photomask using model-based fracturing techniques with charged particle beam simulation, and forming the patterns on a substrate such a silicon wafer using the photomask and an optical lithographic process with directional illumination which is optimized for the preferred diagonal direction.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: June 3, 2014
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Larry Lam Chau, Tam Dinh Thanh Nguyen