Patents Examined by Elias Ullah
  • Patent number: 11955470
    Abstract: A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jiwon Kim, Jaeho Ahn, Sungmin Hwang, Joonsung Lim, Sukkang Sung
  • Patent number: 11955415
    Abstract: The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 9, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Thorsten Scharf, Thomas Bemmerl, Martin Gruber, Thorsten Meyer, Frank Singer
  • Patent number: 11957040
    Abstract: The present disclosure relates to a display panel and a curved display device. The display panel includes a flexible substrate (100), including a first region (BB) and a second region (AA). The first region (BB) includes: a plurality of light emitting structures (110) with a first opening gap (200) formed between two adjacent light omitting structures (110); and a plurality of flexible bridging parts (120), with at least one flexible bridging part (120) connecting two adjacent light emitting structures (110).
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 9, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Long Han
  • Patent number: 11948872
    Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongyoun Kim, Minjun Bae, Hyeonseok Lee, Gwangjae Jeon
  • Patent number: 11942411
    Abstract: RC-IGBT chips and RC-IGBT chips correspond to a pair of adjacent RC-IGBT chips in an X direction between the RC-IGBT chips. The RC-IGBT chips satisfy a first arrangement condition in which the chips are separately arranged without a bonding point region and a bonding point region overlapping each other in a Y direction, and a second arrangement condition in which, in the Y direction, the chips are arranged to partially overlap so that a part of emitter electrodes excluding the bonding point region and the bonding point region overlap. The RC-IGBT chips also satisfy the first and second arrangement conditions described above.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takamasa Miyazaki, Keisuke Eguchi
  • Patent number: 11942448
    Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bo-Hsun Pan, Hung-Yu Chou, Chung-Hao Lin, Yuh-Harng Chien
  • Patent number: 11942758
    Abstract: A manufacturing method comprises: a material preparation step of forming a metal layer on a front side surface of a submount bar body which is to face a laser bar on which a front side electrode and a back side electrode are formed, to prepare a submount bar on which the laser bar is to be mounted; a jig installation step of installing the submount bar and the laser bar that are provided in plural number alternately stacked each other on an installation jig; a bonding step of bonding the metal layer and the back side electrode by increasing the temperature of the installation jig; and a protective film forming step of forming a protective film on cleaved end faces of the laser bar in a protective film forming apparatus using the installation jig in which the submount bars and the laser bars are installed, after the bonding step.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: March 26, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinji Abe
  • Patent number: 11935933
    Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak, Kimin Jun
  • Patent number: 11929347
    Abstract: Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: March 12, 2024
    Assignee: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Patent number: 11923344
    Abstract: A power module is provided with a substrate, power devices, and a housing. The power devices are mounted on device pads of the substrate and arranged to provide a power circuit having a first input, a second input, and at least one output. First and second power terminals provide first and second inputs for the power circuit. At least one output power terminal provides at least one output. The housing encompasses the substrate, the power devices, and portions of the first and second input power terminals as well as the at least one output power terminal. The first and second input power terminals extend out of a first side of the housing, and the at least one output power terminal extends out of a second side of the housing, the first side being opposite the second side.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 5, 2024
    Assignee: WOLFSPEED, INC.
    Inventors: Brice McPherson, Shashwat Singh, Roberto M. Schupbach
  • Patent number: 11917931
    Abstract: The invention relates to a Gunn diode comprising a first contact layer (110); a second contact layer (120); an active layer (130) based on a gallium nitride (GaN)-based semiconductor material, said active layer being formed between the first contact layer (110) and the second contact layer (120); a substrate (140) on which the active layer (130) is formed together with the first contact layer (110) and the second contact layer (120); and an optical inlet (150) for a laser (50) in order to facilitate or trigger a charge carrier transfer between extrema (210, 220) of the energy bands of the active layer (130) by means of laser irradiation.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 27, 2024
    Assignee: Technische Universität Darmstadt
    Inventors: Oktay Yilmazoglu, Ahid S. Hajo
  • Patent number: 11908695
    Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11908686
    Abstract: The present application provides methods for manufacturing a vertical device. To begin with, a GaN-based semiconductor substrate is etched from a front surface to form a trench. Then, a P-type semiconductor layer and an N-type semiconductor layer are sequentially formed on a bottom wall and side walls of the trench and the front surface of the semiconductor substrate. The trench is partially filled with the P-type semiconductor layer. Thereafter, the N-type semiconductor layer and the P-type semiconductor layer are planarized, and the P-type semiconductor layer and the N-type semiconductor layer in the trench are retained. Next, a gate structure is formed at a gate area of the front surface of the semiconductor substrate, a source electrode is formed on two sides of the gate structure, and a drain electrode is formed on a rear surface of the semiconductor substrate respectively.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 20, 2024
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11908825
    Abstract: A semiconductor package includes a lower semiconductor die and an upper semiconductor die which are stacked with an offset in a first direction, wherein the lower semiconductor die includes a plurality of lower pads arranged in a second direction, which is perpendicular to the first direction, and wherein the upper semiconductor die includes a plurality of upper pads arranged in the second direction. The semiconductor package also includes bent wires electrically connecting the lower pads of the lower semiconductor die with the upper pads of the upper semiconductor die in the first direction. The semiconductor package further includes vertical wires such that a vertical wire is disposed on any one of the lower pad and the upper pad for each pair of pads electrically connected by a bent wire.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventor: Jeong Hyun Park
  • Patent number: 11901256
    Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
  • Patent number: 11901345
    Abstract: A semiconductor package may include: a substrate; a first sub-semiconductor package disposed over the substrate, the first sub-semiconductor package including a first buffer chip and a first memory chip; and a second memory chip disposed over the first sub-semiconductor package, wherein the first buffer chip and the first memory chip are connected to each other using a first redistribution line, and wherein the first buffer chip and the second memory chip are connected to each other using a second bonding wire.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 13, 2024
    Assignee: SK hynix Inc.
    Inventors: Jeong Hyun Park, Bok Kyu Choi
  • Patent number: 11901300
    Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: February 13, 2024
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Brian C. Gaide
  • Patent number: 11895890
    Abstract: A display substrate includes a first base and a plurality of pixel units arranged in rows and in columns. A pixel unit includes a first light-emitting device, a second light-emitting device and a third light-emitting device. A first effective light-emitting area where the first light-emitting device is located and a second effective light-emitting area where the second light-emitting device is located are arranged at intervals along a first direction, a third effective light-emitting area where the third light-emitting device is located is spaced apart from both the first effective light-emitting area and the second effective light-emitting area arranged along a second direction.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 6, 2024
    Assignees: HEFEI BOE JOINT TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhidong Yuan, Yongqian Li, Can Yuan
  • Patent number: 11889707
    Abstract: An organic light-emitting diode (OLED) display substrate, a manufacturing method thereof and a display panel are provided. The OLED display substrate has pixel regions and includes a base substrate and a pixel defining layer disposed on the base substrate; in regions of the pixel defining layer corresponding to the pixel regions, accommodation parts penetrating the pixel defining layer are disposed, and the pixel defining layer is further provided with guide parts disposed corresponding to the accommodation parts, the guide parts are located on a periphery of the corresponding accommodation parts and formed by recessed areas which are formed on a side of the pixel defining layer away from the base substrate, the recessed areas do not penetrate the pixel defining layer, and an orthographic projection of the guide part on the base substrate is directly coupled to an orthographic projection of the corresponding accommodation part on the base substrate.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: January 30, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song, Yicheng Lin, Xing Zhang, Pan Xu, Ling Wang, Ying Han
  • Patent number: 11887902
    Abstract: A first wiring member bends at a first bent portion in the shape of the letter “L” in a side view and includes a first horizontal portion parallel to the principal surface of a semiconductor chip and a first vertical portion perpendicular to the first horizontal portion. A second wiring member bends at a second bent portion in a direction opposite to the first wiring member in the shape of the letter “L” in the side view and includes a second horizontal portion flush with the first horizontal portion and a second vertical portion a determined distance distant from the first vertical portion and parallel to the first vertical portion. A wiring holding portion fills a gap between the first and second vertical portions and a gap between the first and second bent portions. Therefore, stress applied to the vicinity of the first or second bent portion is relaxed.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: January 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Satoshi Kaneko