Abstract: A package substrate includes; a conductive line extending in a first horizontal direction, a conductive pad on an upper surface of the package substrate and horizontally spaced apart from the conductive line in a second horizontal direction, and a protective layer covering the conductive line and including an opening selectively exposing a portion of the conductive pad. The opening has an elongated elliptical shape having a minor axis defined by a width extending in the first horizontal direction and a major axis defined by a length extending in the second horizontal direction.

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality of gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.

Abstract: A light-emitting substrate, a method of manufacturing a light-emitting substrate, and a display device are provided. The light-emitting substrate includes: a first substrate, wherein the first substrate includes a first base substrate, a light-emitting diode arranged on the first base substrate, and a first conductive pad arranged on the first base substrate; a second substrate arranged opposite to the first substrate, wherein the second substrate includes a second base substrate, and a second conductive pad arranged on the second base substrate; and a bonding wire structure including a bonding wire, wherein the first conductive pad is located on a surface of the first substrate away from the second substrate, the second conductive pad is located on a surface of the second substrate away from the first substrate, and the bonding wire is configured to electrically connect the first conductive pad and the second conductive pad.

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

Abstract: A light emitting device includes a printed circuit board (PCB) including a connection pad, a base substrate mounted on the PCB and including a pixel region and a pad region, light emitting structures arranged on the pixel region, a barrier rib structure disposed on the pixel region and disposed at a vertical level different from the light emitting structures, the barrier rib structure including barrier ribs connected with each other to define each of pixel spaces, a phosphor layer filling each pixel space, a dam structure surrounding the barrier rib structure, a pad disposed on the pad region and adjacent to at least one side of an outer boundary of the light emitting structures, a bonding wire connecting the connection pad to the pad, and a molding structure covering the pad, the connection pad, the bonding wire, and at least a portion of the dam structure.

Abstract: Provided is a display substrate. The display includes a base substrate, and a pixel unit disposed on the base substrate, wherein the pixel unit includes a storage capacitor, a plate of the storage capacitor being a transparent plate. The pixel unit further comprises an active layer and a source/drain pattern, which are disposed in two different layers.

Abstract: A semiconductor element including: an element substrate provided with an element region at a middle part and a peripheral region outside the element region; and a readout circuit substrate facing the element substrate, in which the element substrate includes a first semiconductor layer provided in the element region and including a compound semiconductor material, a wiring layer provided between the first semiconductor layer and the readout circuit substrate, the wiring layer electrically coupling the first semiconductor layer and the readout circuit substrate to each other, a first passivation film provided between the wiring layer and the first semiconductor layer, and a second passivation film opposed to the first passivation film with the first semiconductor layer interposed therebetween, and in which the peripheral region of the element substrate includes a bonded surface with respect to the readout circuit substrate.

Abstract: A light-emitting device includes a substrate, multiple light-emitting units that are disposed on the substrate, that are spaced apart by an isolation trench and that are and electrically interconnected by an interconnecting structure, and an insulating layer with thickness of 200 nm to 450 nm. A potential difference between adjacent two light-emitting units not in direct electrical connection is at least two times forward voltage of each of the light-emitting units. Each light-emitting unit includes a light-emitting stack and a light-transmissible current spreading layer. The insulating layer covers the light-transmissible current spreading layers and at least a part of the light-emitting stacks.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes an array substrate, a bonding area of the array substrate is provided with a plurality of bonding pads and a driving chip. A first area of the driving chip is at least provided with a plurality of first dummy terminals. A height difference caused by warping of driving terminals can be compensated by the first dummy terminals, thereby avoiding a phenomenon of shallow conduction. An insulation protective layer is provided on a part of the array substrate which is corresponding to the first dummy terminals, thereby preventing metal wirings from extrusion damage.

Abstract: A display device includes a first substrate including a display area, a non-display area, and a plurality of pixel circuit units in the display area and the non-display area, a plurality of light emitting elements on the first substrate in the display area, the plurality of light emitting elements being electrically connected to the pixel circuit units, a hole mask layer on the first substrate and including a plurality of holes corresponding to the light emitting elements, a second substrate on the hole mask layer and including a plurality of open holes corresponding to the plurality of holes, and a plurality of light exit patterns in the plurality of the open holes of the second substrate corresponding to the plurality of holes, wherein each of the light exit patterns includes a first part in one of the plurality of open holes.

Abstract: A light-emitting diode (LED) unit for a display including a plurality of pixels each including a first light emitting cell, a second light emitting cell, and a third light emitting cell, each of the first, second, and third light emitting cells including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, a first wavelength converter configured to convert a wavelength of light emitted from the first light emitting cell, a second wavelength converter configured to convert a wavelength of light emitted from the second light emitting cell, in which the first, second, and third light emitting cells of each pixel share the first conductivity type semiconductor layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.

Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.

Abstract: The MEMS actuator is formed by a body, which surrounds a cavity and by a deformable structure, which is suspended on the cavity and is formed by a movable portion and by a plurality of deformable elements. The deformable elements are arranged consecutively to each other, connect the movable portion to the body and are each subject to a deformation. The MEMS actuator further comprises at least one plurality of actuation structures, which are supported by the deformable elements and are configured to cause a translation of the movable portion greater than the deformation of each deformable element. The actuation structures each have a respective first piezoelectric region.

Abstract: A light-emitting diode includes a first semiconductor region having a first conductive type; a second semiconductor region having a second conductive type; and an active layer disposed between the first semiconductor region and the second semiconductor region and including phosphorus (P). The light-emitting diode has a rod shape, the second semiconductor region includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer, which are sequentially stacked, the first semiconductor layer is disposed between the active layer and the second semiconductor layer, and the second semiconductor layer includes a compound represented by AlGaInP and satisfying Equation 1.

Abstract: A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

Abstract: A TSV of a first semiconductor die may extend from a semiconductor substrate of the first semiconductor die through at least one metallization layer of the die to connect to a metallization layer to supply power to the second semiconductor die. By extending the TSV, resistance may be reduced, allowing for enhanced power delivery to the second semiconductor die. Resistance may be further reduced by allowing for the TSV to connect to a thicker metallization layer than would otherwise be possible. Also, in some embodiments, the TSV may connect to a metallization layer that is suitable for supplying power to both semiconductor dies. The first semiconductor die may be a top die or a bottom die in a face-to-face arrangement. Disclosed concepts may be extended to any number of dies included in a die stack that includes the face-to-face arrangement.

Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.

Abstract: Abnormal generation of heat of a power MOSFET is detected to improve the reliability of a semiconductor device. As its means, in a power MOSFET having a drain electrode on the side of a back surface of a semiconductor substrate and a source pad on the side of a main surface of the semiconductor substrate, two gate pads electrically connected to a gate pad connected to a gate electrode of the power MOSFET are formed on the side of the main surface of the semiconductor substrate. Further, there is provided a voltmeter connected in parallel with each of two current paths which connect the two gate pads and a gate driver.

Abstract: Provided is a display substrate. The display substrate includes a base substrate, and a pixel unit disposed on the base substrate. The pixel unit includes a storage capacitor, the storage capacitor includes a first plate and a second plate facing each other, and a plate of the storage capacitor is a transparent plate. The pixel unit further includes an active layer and a source/drain pattern, which are disposed in two different layers.