Abstract: The present disclosure relates to an organic light-emitting display substrate, manufacturing method thereof, and organic light-emitting display device. The organic light-emitting display substrate includes a base and a plurality of sub-pixel structures on the base, the sub-pixel structure includes: a first protrusion including a photoelectric sensing device and a second protrusion including a color filter layer, a protrusion height of the first protrusion relative to the base being smaller than that of the second protrusion relative to the base; a planarization layer on the first and second protrusions, and in contact with the first and second protrusions, a material wettability of the planarization layer with respect to the surface of the first protrusion being greater than that with respect to the surface of the second protrusion; and a white organic light-emitting diode on the planarization layer, and emitting light towards the first and second protrusions.

Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.

Abstract: According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w<Wth, where s is a thickness of the buffer layer, t is a thickness of the electrode, and Wth=2×(s×t?s2)0.5 holds true.

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

Abstract: Provided herein include various examples of an apparatus, a sensor system and examples of a method for manufacturing aspects of an apparatus, a sensor system. The apparatus may include a die. The apparatus may also include a substrate comprising a cavity. The die may be oriented in a portion of the cavity in the substrate, where the orientation defines a first space in the cavity adjacent to a first edge of the upper surface of the die and a second space in the cavity adjacent to the second edge of the upper surface of the die. The apparatus may further include fluidics fan-out regions comprising a first cured material deposited in the first space and the second space, a surface of the fluidics fan-out regions being contiguous with the upper surface of the die.

Abstract: In the display device according to the disclosure, a first bank includes a first bank lower portion in the same layer as a flattening film and a first bank upper portion in the same layer as an edge cover. A second bank includes a second bank lower portion in the same layer as the flattening film and a second bank upper portion in the same layer as the edge cover. The first bank upper portion covers an upper surface and a side surface of the first bank lower portion, the side surface being on a side close to a display region. An inclination angle of a side surface of the first bank upper portion on a side close to the display region is larger than an inclination angle of the side surface of the first bank lower portion on the side close to the display region.

Abstract: A semiconductor-module external terminal includes a bottom portion to be soldered and a terminal body vertically bent from the bottom portion, and the terminal body includes a first groove on a left end side and a second groove on a right end side of a bending portion which is bent immediately above the bottom portion, and the first groove and the second groove are asymmetrical with respect to a center line passing the terminal body in a vertical direction.

Abstract: A semiconductor device includes: an insulating substrate; a first semiconductor element connected to the insulating substrate; a conductive member disposed on the insulating substrate, and including a first opposing portion and a second opposing portion located opposite each other with respect to the first semiconductor element in plan view; a first wire connected to the first semiconductor element and the first opposing portion; and a second wire connected to the first semiconductor element and the second opposing portion, and located opposite the first wire with respect to a connection point where the first wire and the first semiconductor element are connected to each other in plan view.

Abstract: A system configured to increase a reliability of electrical connections in a device. The system including a lead configured to electrically connect a pad of at least one support structure to a pad of at least one electrical component. The lead includes an upper portion that includes a lower surface arranged on a lower surface thereof. The lower surface of the upper portion is arranged vertically above a first upper surface of a first pad connection portion; and the lower surface of the upper portion is arranged vertically above a second upper surface of the second pad connection portion. A process configured to increase a reliability of electrical connections in a device is also disclosed.

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

Abstract: A light emitting device for a display including: a base layer; a first LED sub-unit, a second LED sub-unit, and a third LED sub-unit on the base layer; and a supporting layer covering the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit, in which the third LED sub-unit is configured to emit light having a shorter wavelength than that of light emitted from the first LED sub-unit, and to emit light having a longer wavelength than that of light emitted from the second LED sub-unit, and a luminous intensity ratio of light emitted from the third LED sub-unit and the second LED sub-unit is configured to be about 6:1.

Abstract: A light-emitting diode (LED) unit for a display including a plurality of pixels each including a first light emitting cell, a second light emitting cell, and a third light emitting cell, each of the first, second, and third light emitting cells including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, a first wavelength converter configured to convert a wavelength of light emitted from the first light emitting cell, a second wavelength converter configured to convert a wavelength of light emitted from the second light emitting cell, in which the first, second, and third light emitting cells of each pixel share the first conductivity type semiconductor layer.

Abstract: A no-gel sensor package is disclosed. In one embodiment, the package includes a microelectromechanical system (MEMS) die having a first substrate, which in turn includes a first surface on which is formed a MEMS device. The package also includes a polymer ring with an inner wall extending between first and second oppositely facing surfaces. The first surface of the polymer ring is bonded to the first surface of the first substrate to define a first cavity in which the MEMS device is contained. A molded compound body having a second cavity that is concentric with the first cavity, enables fluid communication between the MEMS device and an environment external to the package.

Abstract: An electronic structure, an electronic package structure and method of manufacturing an electronic device are provided. The electronic structure includes a carrier and a protection layer. The carrier includes a first pad, a second pad and a first dielectric layer. The first pad is at a side of the carrier and configured to bond with a conductive pad. The second pad is at the side of carrier and configured to electrically connect an exterior circuit. The first dielectric layer includes a first portion around the first pad and a second portion around the second pad, wherein a top surface of the first portion and a top surface of the second portion are substantially coplanar. The protection layer is on the second pad and covers the second pad.

Abstract: An optical coupling structures are disposed on light output surfaces of semiconductor LEDs of a miniLED or microLED array to facilitate coupling of light emitted by the semiconductor LEDs through the light output surfaces. The optical coupling structures comprise light scattering particles and/or air voids embedded in or coated with a thin layer of a material that has an index of refraction close to or matching the index of refraction of the material forming the light output surface of the semiconductor LEDs.

Abstract: An object of the present invention is to suppress electrical contact between an outer peripheral portion of an intermediate electrode and a front surface electrode of a semiconductor chip without increasing the area of the semiconductor chip. A facing surface of the first intermediate electrode facing a first main electrode is smaller than a facing surface of the first main electrode facing the first intermediate electrode, and has an outer peripheral protective region and a connection region surrounded by the protective region. A pressure-contact semiconductor device includes a plurality of first conductor films partially formed in the connection region, and a first insulating film formed in regions in the connection region where no first conductor films are formed and in the protective region.

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.