Abstract: A semiconductor module includes: a dissipating metal plate including a recess provided on an upper surface; an insulating substrate provided on a bottom surface of the recess and including a circuit pattern; a semiconductor device provided on the insulating substrate and connected to the circuit pattern; a case bonded to a peripheral portion on the upper surface of the dissipating metal plate and surrounding the insulating substrate and the semiconductor device; a case electrode provided on the case; a wire connecting the semiconductor device and the case electrode; and a sealant provided in the case and sealing the insulating substrate, the semiconductor device, and the wire, wherein a sidewall of the recess has a taper.

Abstract: A light emitting device module includes a substrate, a plurality of light emitting devices mounted on the substrate, an adhesive layer interposed between the substrate and the light emitting device; and bonding wires electrically connecting the plurality of light emitting devices. The substrate includes an outer electrode in at least a partial region, and the adhesive layer has a non-conductive material.

Abstract: A semiconductor device includes: a first power supply terminal; a second power supply terminal; an output terminal; a first switching element connected between the first power supply terminal and the output terminal; and a second switching element connected between the second power supply terminal and the output terminal. The first power supply terminal includes: a first facing portion; a second facing portion; and a third facing portion. The first facing portion and the second facing portion are provided such that, upon application of a current, the current flows through the first facing portion and the second facing portion in a direction opposite to a direction in which the current flows through each of portions in the second power supply terminal that face the first facing portion and the second facing portion.

Abstract: A power module package is provided. The power module package may include: a first substrate; a second substrate; a semiconductor chip disposed between the first substrate and the second substrate; and a mutual-connection layer that is formed between the semiconductor chip and the second substrate and provides conductive connection between the semiconductor chip and the second substrate.

Abstract: The disclosed embodiments generally relate to a method, system and apparatus for forming a custom-sized display panel. An exemplary method to form a custom display from a large sheet of pixels includes: providing a sheet of pixels having a TFT substrate, a liquid crystal layer and a second substrate, the sheet of pixels having a first perimeter, the liquid crystal medium interposed between the TFT substrate and the second substrate; forming a display panel from the sheet of pixels, the display panel having a display panel perimeter, the second display having a first edge defined by the TFT substrate extending beyond the second substrate to thereby expose an electrical trace on the TFT substrate; sealing the liquid crystal layer on the first edge; conductively exposing the electrical trace on the TFT substrate; and forming a column driver line on the TFT substrate to communicate a driver signal to the second display.

Abstract: Provided is a semiconductor module including: an insulating circuit board that includes an insulating board and a conductive circuit pattern provided on an upper surface of the insulating board; a semiconductor chip that is provided above the insulating circuit board; a solder portion that bonds the circuit pattern and the semiconductor chip; and one or more temperature gradient adjustment portions configured to be bonded to the insulating circuit board and have at least one surface disposed to face at least one surface of the solder portion. The insulating circuit board is warped in a first direction. At least one of the temperature gradient adjustment portions is disposed at a place where an amount of warpage of the insulating circuit board in the first direction is smaller than an average amount of warpage of the insulating circuit board in the first direction.

Abstract: Provided is a semiconductor device including a first n-type transistor comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second n-type transistor comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.

Abstract: A semiconductor device includes a first stacked body including a plurality of first semiconductor chips stacked along a first direction, each of the first semiconductor chips being offset from the other first semiconductor chips along a second direction perpendicular to the first direction; a first columnar electrode connected to an electrode pad of the first stacked body, and extending in the first direction; a second stacked body including a plurality of second semiconductor chips stacked along the first direction, each of the second semiconductor chips being offset from the other second semiconductor chips along the second direction, the second stacked body having a height larger than the first stacked body and overlap at least a portion of the first stacked body when viewed from the top; and a second columnar electrode connected to an electrode pad of the second stacked body, and extending in the first direction.

Abstract: A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer.

Abstract: An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.

Abstract: A method of manufacturing a channel all-around semiconductor device includes: forming a plurality of gate structures having the same extension direction, and forming a multi-connected channel layer on a substrate. Each of the gate structures has opposite first end and second end, and the gate structures are all surrounded by the formed multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the extension direction of the gate structures, so that channels of the gate structures are connected to each other.

Abstract: A semiconductor module includes a semiconductor element, a substrate on which the semiconductor module is mounted, a heat radiating plate on which the substrate is mounted, a resin case, and a first main current electrode and a second main current electrode, in which in the first main current electrode and the second main current electrode, one end of each thereof is joined to a circuit pattern on the substrate, an other end of each thereof is extended through and incorporated in a side wall of the resin case so as to project outward of the resin case, and each thereof has at least a portion of overlap at which a part thereof overlaps in parallel with each other with a gap therebetween, and each thereof has a slope portion provided between an external projection portion and an internal projection portion.

Abstract: Provided is a package structure includes a first die, a first dielectric layer, a second dielectric layer and a carrier. The first dielectric layer covers a bottom surface of the first die. The first dielectric layer includes a first edge portion and a first center portion in contact with the bottom surface of the first die. The second dielectric layer is disposed on the first dielectric layer and laterally surrounding the first die. The second dielectric layer includes a second edge portion and a second center portion. The second edge portion is located on the first edge portion, and the second edge portion is thinner than the second center portion. The carrier is bonded to the first dielectric layer through a bonding film.

Abstract: A power semiconductor module arrangement includes: a housing; first and second electrical contacts within the housing; and a mounting arrangement including a frame or body and first and second terminal elements. The mounting arrangement is inserted in and coupled to the housing. First ends of the first and second terminal elements mechanically and electrically contact the first and second electrical contacts, respectively. A middle part of each terminal element extends through the frame or body. A second end of each terminal element extends outside the housing. The first terminal element is dielectrically insulated from the second terminal element by a portion of the frame or body. The first terminal element is injected into and inextricably coupled to the frame or body. The second terminal element is arranged within a hollow space inside the frame or body and is detachably coupled to the frame or body.

Abstract: One example of a pre-molded lead frame includes a mold body, a plurality of recesses, and a plurality of first leads. The mold body includes a first main surface and a second main surface opposite to the first main surface. Each recess of the plurality of recesses extends from the first main surface into the mold body. The plurality of first leads are coupled to the mold body and extend from a third surface of the mold body. The third surface extends between the first main surface and the second main surface.

Abstract: A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.

Abstract: A semiconductor package includes a substrate, a semiconductor die mounted on the substrate, and a heatsink over the semiconductor die. The heatsink includes a roof portion and at least one connecting portion extending between the roof portion and the substrate. The at least one connecting portion includes a connection lead mounted on a connection pad of the substrate. The connection pad includes a first portion and a second portion spaced apart from each other, which are configured to electrically couple to different voltage signals, respectively, for detecting heatsink floating.

Abstract: An RF transistor package includes a metal submount; a transistor die mounted to the metal submount; and a surface mount IPD component mounted to the metal submount. The surface mount IPD component includes a dielectric substrate that includes a top surface and a bottom surface and at least a first pad and a second pad arranged on a top surface of the surface mount IPD component; at least one surface mount device includes a first terminal and a second terminal, the first terminal of the surface mount device mounted to the first pad and the second terminal mounted to the second pad; at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by the dielectric substrate; and at least one wire bond bonded to the at least one of the first pad and the second pad.

Abstract: An electronic device includes: a substrate; a first electronic component that is mounted on a first surface of the substrate; a cap that accommodates the first electronic component between the cap and the substrate; and a mold portion that bonds the cap and the substrate. The cap includes a base portion having a recess that opens to a substrate side and accommodates the first electronic component, and a flange portion that protrudes from an end portion of the base portion on the substrate side to an outer peripheral side and is in contact with the first surface. The mold portion is provided from a second surface side of the substrate to a first surface side while bypassing a side, and bonds the cap and the substrate by molding the flange portion in a portion on the first surface side.

Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.