Abstract: Systems and methods are provided for an accelerator system that includes a baseline (production) accelerator, optimizing accelerator, and control hardware accelerator, and an operation of alternatingly switching the production/optimizing accelerators between production and optimizing. With two production/optimizing accelerators, at any given point in time, one accelerator adapts while another accelerator processes data. Once the second accelerator starts doing a better job (e.g., has adapted to data drift), the accelerators change their modes, and the trainable accelerator becomes the “optimized” one. The accelerators do this non-stop, thus maintaining redundancy, providing expected quality of service (QoS) and adapting to data/concept drift.

Abstract: A failure analysis and detection method for a memory is configured to perform abnormal bit detection on a memory. The failure analysis and detection method includes: coordinates are marked on a detection area of the memory, and the coordinates are associated with layout design or a process of the detection area; a MOD function is used to perform classification according to regularity of the coordinates, and the MOD function is a function for getting remainder; and failure information corresponding to the classification is obtained from a failure bitmap (FBM) of the detection area, and the failure information includes a failure cause corresponding to the layout design or the process.

Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.

Abstract: A method of operating a digital radio receiver is provided as follows: a) receiving a radio signal comprising a symbol sequence; b) selecting a portion of the symbol sequence; c) determining a first error between the selected portion of the symbol sequence and a first predetermined symbol sequence using a difference metric; d) determining a set of second errors between the selected portion of the symbol sequence and a respective set of second predetermined symbol sequences, each formed by prepending different length portions of a predetermined preamble symbol sequence to a beginning of the first predetermined symbol sequence; and e) determining a minimum error from the first error and the set of second errors. If the first error is not the minimum error, a different portion of the symbol sequence is selected. Otherwise, a following portion of the symbol sequence is decoded to produce a data payload.

Abstract: A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.

Abstract: Systems and methods for more efficiently decoding convolutional LDPC encoded communication signals are described. A decoder circuit iteratively determines the values of received data bits and confidence values corresponding to the determined data bit values. Using the confidence values and one or both of check fail counters and log likelihood ratio (LLR) sign changes, the decoder circuit can determine that a desired level of confidence has been satisfied and can subsequently terminate decoding operations to save power.

Abstract: A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate write data and write parity from write input data when a write operation in an operation mode is performed, and generate converted data from read data and read parity when a read operation in an operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the converted data and buffer data to generate MAC operation result data.

Abstract: A processing-in-memory (PIM) device includes an CRC logic circuit configured to generate first write data, a first write fail check signal, second write data, and a second write fail check signal from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data, a first fail flag signal, second converted data, and a second fail flag signal from first read data, a first read fail check signal, second read data, and a second read fail check signal when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data, based on the first and second fail flag signals to generate MAC operation result data.

Abstract: An apparatus that includes a memory cell array, an I/O terminal supplied with an original write data in a normal operation, a compression logic circuit configured to generate a compressed test data in a test operation based on a test read data read from the memory cell array, and a syndrome generator configured to generate a first syndrome based on the original write data in the normal operation and generate a second syndrome based on the compressed test data in the test operation.

Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

Abstract: Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.

Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.

Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.

Abstract: A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data.

Abstract: A method for execution by one or more modules of one or more processors of a storage network includes receiving a data object for storage, segmenting the data object into a plurality of data segments and determining a level of security and a level of performance for the plurality of data segments. The method continues by determining whether one or more data segments of the plurality of data segments is to be transformed using an all-or-nothing transformation and in response to a determination to transform one or more data segments of the plurality of data segments, transforming a data segment of the plurality of data segments to produce a transformed data segment. The method continues by dispersed error encoding the transformed data segment to produce a set of encoded data slices and transmitting the set of encoded data slices to a set of storage units of the storage network.

Abstract: A read-disturb-based read temperature time-based attenuation system includes a storage device that is coupled to a global read temperature identification subsystem. The storage device determines current read disturb information for data stored in a block in the storage device during a current time period, processes the current read disturb information and previous read disturb information that was determined during at least one previous time period that was prior to the current time period in order to generate a read temperature for the data stored in the block, generates a local logical storage element read temperature map that includes the read temperature, and provides the local logical storage element map to the global read temperature identification subsystem.

Abstract: Mechanisms are provided to receive encoded header information stored on a tape of a tape drive, wherein the encoded header information has been generated by: generating, for a plurality of tracks of the tape of the tape drive, a header information in a plurality of symbols, wherein the plurality of symbols is comprised of a first set of symbols and a second set of symbols, wherein the first set of symbols include identical information across all tracks of the plurality of tracks, and wherein the second set of symbols are configurable to include different information across all tracks of the plurality of tracks; and modifying, for writing to the tape of the tape drive, the first set of symbols of the plurality of tracks to include parity information corresponding to information included in the second set of symbols of the plurality of tracks. The received encoded header information is decoded.

Abstract: Exemplary methods, apparatuses, and systems include a media temperature manager receiving operating temperature measurements for a memory subsystem. The media temperature manager generates an average temperature using the operating temperature measurements. The media temperature manager determines that the average temperature satisfies a first value for a dynamic temperature threshold. The dynamic temperature threshold indicates a temperature at which the memory subsystem throttles media operations. The media temperature manager increases the dynamic temperature threshold to a second value in response to the average temperature satisfying the first value for the dynamic temperature threshold.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: The embodiments herein provide a system and method for generating a catalog of graphs that acts as a source for creating error correcting codes. A D3 chord index notation is used to describe the graphs. A list of (3, g) Hamiltonian graphs for even girth g is created to satisfy the condition 6?g?16. Each of the lists is infinite and is used for creating LDPC codes of high quality.