Patents Examined by Enam Ahmed
  • Patent number: 11316535
    Abstract: An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 26, 2022
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 11309914
    Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 19, 2022
    Inventors: Se-ho Myung, Belkacem Mouhouche, Daniel Ansorregui Lobete, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11309046
    Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an error check enablement signal, an input clock signal, and input data to the second semiconductor device. The first semiconductor device receives an error check signal from the second semiconductor device. The second semiconductor device performs an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal which is enabled when an error in the input data occurs.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Sun Myung Choi
  • Patent number: 11301323
    Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: April 12, 2022
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wang, Ara Patapoutian, Bengt Anders Ulriksson
  • Patent number: 11296834
    Abstract: A method of operating a transmission system (1) having a first network (2) and at least one second network (3) where data is exchanged in that data of the first network (2) is inputted between these at least two networks (2, 3) into duplication means (4), and the inputted data is transmitted wirelessly via at least two transmission paths (6, 7) using PRP to separator means (5) and forwarded from the separating means (5) to the connected second network (3), characterized in that the data is transmitted as data packets and each data packet is transmitted several times via the same transmission path (6, 7).
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: April 5, 2022
    Inventor: Tobias Heer
  • Patent number: 11283467
    Abstract: A network interface groups and encodes a plurality of bits into a plurality of bit blocks such that a number of bits within the fixed-length frame are available for use as parity bits in a fixed-length frame. The network interface device aggregates a first set of bit blocks and a second set of bit blocks into an aggregated bit block, and encodes a portion of the aggregated bit block using a first encoder to generate a first set of encoded bits according to a first error correction encoding scheme. The network interface device encodes a remaining portion of the aggregated bit block using a second encoder to generate a second set of encoded bits according to a second error correction encoding scheme. A number of parity bits generated by the first and second encoders does not exceed the number of bits in the fixed-length frame made available for use as parity bits.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 22, 2022
    Assignee: Marvell Asia Pte Ltd
    Inventor: William Lo
  • Patent number: 11269721
    Abstract: A memory system apparatus may be provided. The memory system may have memory controller. The memory controller may be configured to perform a scrambling operation before an error correction code (ECC) operation is performed.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Soojin Kim
  • Patent number: 11269724
    Abstract: A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 8, 2022
    Inventor: Jong-Wook Park
  • Patent number: 11264098
    Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: March 1, 2022
    Inventors: Shinya Koizumi, Kiyotaka Iwasaki
  • Patent number: 11256563
    Abstract: A memory controller including: a fault determination circuit to receive first parity, second parity, and data read out from a first row of a memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit to store a repair parity for repairing a fault of a row of a plurality of rows of the memory device, wherein the plurality of rows constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; and a recovery circuit to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: February 22, 2022
    Inventors: Jeongho Lee, Youngjin Cho, Seungwon Lee
  • Patent number: 11233530
    Abstract: Wireless communication devices are adapted to facilitate information sequences included in frozen sub-channels of polar coded transmissions. According to one example, an apparatus can generate a mask sequence based on a plurality of parameters, including at least one of a transmitting-device-specific sequence or a receiving-device-specific sequence. In some examples, the frozen bits may be masked with the mask sequence, and an information block may be encoded utilizing polar coding. In other examples, the mask sequence may be compared to the frozen bits of a received information block, and the received information block may be determined as intended for the apparatus when the mask sequence matches to the frozen bits. Other aspects, embodiments, and features are also included.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 25, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Gaojin Wu, Chao Wei, Jing Jiang
  • Patent number: 11233643
    Abstract: A method for execution by a processing module of a distributed storage includes transmitting a request to retrieve a set of encoded data slices (EDSs) to a plurality of storage nodes followed by receiving a threshold number of EDSs from one or more of the plurality of storage nodes, and decoding the EDSs to produce a transposed encrypted data segment. The method continues with the processing module partitioning the encrypted data segment into an encoded encryption key and encrypted data, performing a hash function on the encrypted data to produce a digest resultant and combining the digest resultant with the encoded encryption key to generate combined key data. The method then continues with decoding the combined key data to recover an encryption key and decrypting the encrypted data using the encryption key to recover a data segment.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 25, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Wesley B. Leggette, Jason K. Resch
  • Patent number: 11218164
    Abstract: Uncorrectable (UNC) marking on a non-volatile memory is provided. In response to a UNC marking command issued by a host, a cyclic redundancy check (CRC) engine provides a specific CRC code to mark a logical address segment as uncorrectable, wherein the logical address segment is requested to be marked as uncorrectable by the UNC marking command. As long as the specific CRC code is recognized, a CRC procedure is not required and the data requested by the host is directly determined as uncorrectable.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 4, 2022
    Assignee: SILICON MOTION, INC.
    Inventors: Hsuan-Ping Lin, Jie-Hao Lee
  • Patent number: 11201690
    Abstract: A test instrument or host device can apply inverse transmitter and receiver functions to data transmitted or received by an electrical and optical transponder. The inverse transmitter and receiver functions are applied to counteract internal signal conversion processes of the transponder. Forward error correction and test pattern analysis may be performed on signals received from the transponder after the inverse receiver function is applied to the received signals.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: December 14, 2021
    Inventor: Andrew Neal
  • Patent number: 11177909
    Abstract: Various aspects related to ACK/NACK feedback for multi-TRP transmission scenarios are described. A base station, may send, to a UE, information indicating PDCCH monitoring occasions for each of a plurality of TRPs. In one aspect, the base station may send information indicating whether ACK/NACK feedback across the plurality of TRPs is allowed. The base station may send rules to the UE for performing ACK/NACK feedback bundling for providing feedback to the plurality of TRPs. The base station may also send information indicating a DAI definition for interpreting DAIs transmitted by the plurality of TRPs in corresponding PDCCH transmissions indicating whether the DAIs are independent or joint. The base station may receive a joint ACK/NACK feedback from the UE in a PUCCH based on the rules, or may receive multiple ACK/NACK feedback from the UE in a PUCCH for a first TRP independent from a second TRP.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaoxia Zhang, Jing Sun, Tamer Kadous
  • Patent number: 11177906
    Abstract: An LDPC (Low-Density Parity Check) code based on a control matrix represented by a Tanner bipartite graph includes 128 variable nodes of the graph and 64 constraint nodes of the graph, the code being wherein each of the constraint nodes of the graph is connected to 7 variable nodes of the graph; each of the cycles of the graph has a length greater than or equal to 6; the minimum distance of the code is equal to or greater than a predefined threshold for minimum distance.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 16, 2021
    Assignees: SUEZ GROUPE, GRDF
    Inventor: Jean-Louis Dornstetter
  • Patent number: 11163634
    Abstract: An H matrix generating circuit for generating an H matrix of a QC-LDPC code may include: a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; and a shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Chol Su Chae, Jang Seob Kim
  • Patent number: 11159177
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: October 26, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11146289
    Abstract: Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Aman Bhatia, Zion S. Kwok, Justin Kang, Poovaiah M. Palangappa, Santhosh K. Vanaparthy
  • Patent number: 11132251
    Abstract: Generating data checksum for a data object including multiple data units comprises, for each data unit, obtaining a corresponding address of the data unit, and rotating the data unit based on said corresponding address of the data unit to generate a rotated data unit. A checksum value for the data object is determined based on said rotated data units.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: September 28, 2021
    Inventor: Jonathan M. Haswell