Patents Examined by Enam Ahmed
  • Patent number: 11914474
    Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tyler L. Betz, Andrew M. Kowles, Adam J. Hieb
  • Patent number: 11916667
    Abstract: Examples of check codes, methods of creating check codes, and communication systems utilizing check codes, such as low-density parity-check codes (LDPC codes) are described herein. In some examples, check codes described herein utilize a larger number of check operations than check bits.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: February 27, 2024
    Assignee: Tarana Wireless, Inc.
    Inventor: Kelly Davidson Hawkes
  • Patent number: 11892506
    Abstract: A multicycle path circuit capable of operating at a functional mode and an at-speed test mode. The multicycle path circuit includes an on-chip controller configured to receive an on-chip clock signal and modulate the on-chip clock signal to provide a first clock signal to a first circuit and a second clock signal to a second circuit. The first clock signal and the second clock signal are in a multicycle phase relationship. The on-chip controller is configured to ensure the clock paths to and from the second circuit to be the same for the functional mode and the at-speed test mode and therefore to avoid hold and setup timing conflict between these modes.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: February 6, 2024
    Assignee: MEDIATEK Singapore Pte. Ltd.
    Inventors: Ashish Kumar Nayak, Gokulakrishnan Manoharan, Mahesh Kumar Devani
  • Patent number: 11894085
    Abstract: Implementations described herein relate to memory section selection for a memory built-in self-test. A memory device may read a first set of bits stored in a test control mode register. The memory device may identify a test mode, for performing a memory built-in self-test, based on the first set of bits. The memory device may read a second set of bits stored in a section identifier mode register. The memory device may identify one or more memory sections of the memory device, for which the memory built-in self-test is to be performed, based on the second set of bits. The one or more memory sections may be a subset of a plurality of memory sections into which the memory device is divided. The memory device may perform the memory built-in self-test for the one or more memory sections of the memory device based on the test mode.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Schaefer
  • Patent number: 11892916
    Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Christopher Joseph Bueb
  • Patent number: 11886286
    Abstract: Generating data checksum for a data object including multiple data units comprises, for each data unit, obtaining a corresponding address of the data unit, and rotating the data unit based on said corresponding address of the data unit to generate a rotated data unit. A checksum value for the data object is determined based on said rotated data units.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jonathan M. Haswell
  • Patent number: 11886999
    Abstract: Apparatuses and methods can be related to implementing age-based network training. An artificial neural network (ANN) can be trained by introducing errors into the ANN. The errors and the quantity of errors introduced into the ANN can be based on age-based characteristics of the memory device.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Saideep Tiku, Poorna Kale
  • Patent number: 11874734
    Abstract: A method for operating a memory includes: performing an error check operation on first memory cells; performing an error check operation on second memory cells; detecting an error which is equal to or greater than a threshold value in a region including the first memory cells and the second memory cells; classifying the region as a bad region in response to the detection of an error which is equal to or greater than the threshold value; and performing an error check operation on the first memory cells and the second memory cells again in response to the classification of the bad region.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: January 16, 2024
    Assignee: SK hynix Inc.
    Inventors: Dae Suk Kim, Eung Bo Shim
  • Patent number: 11870458
    Abstract: Embodiments herein relate to a method performed by a network node for handling a received signal in a communication network. The network node distributes a first number of inputs of a demodulated signal to a first processing core of at least two processing cores and a second number of inputs of the demodulated signal to a second processing core of the at least two processing cores. The network node further decodes the first number of inputs of the demodulated signal by a first message passing within the first processing core, and decodes the second number of inputs of the demodulated signal by a second message passing within the second processing core. The network node further decodes the demodulated signal by performing a third message passing between the different processing cores over a bus that is performed according to a set schedule.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: January 9, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Hugo Tullberg, Guido Carlo Ferrante
  • Patent number: 11870464
    Abstract: A method of producing a set of coded bits from a set of information bits for transmission between a first node and a second node in a wireless communications system, the method comprises generating a codeword vector by encoding the set of information bits with a low-density parity-check code, wherein the codeword vector is composed of systematic bits and parity bits. The method comprises performing circular buffer-based rate matching on the generated codeword vector to produce the coded bits for transmission, wherein the circular buffer-based rate matching comprises puncturing a first plurality of systematic bits.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: January 9, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Mattias Andersson, Yufei Blankenship, Sara Sandberg
  • Patent number: 11869618
    Abstract: A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Ying Yu Tai, Cheng Yuan Wu, Jiangli Zhu
  • Patent number: 11870459
    Abstract: Described is a decoder suitable for use with any communication or storage system. The described decoder has a modular decoder hardware architecture capable of implementing a noise guessing process and due to its dependency only on noise, the decoder design is independent of any encoder, thus making it a universal decoder. Hence, the decoder architecture described herein is agnostic to any coding scheme.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 9, 2024
    Assignees: Massachusetts Institute of Technology, National University of Ireland Maynooth, Trustees of Boston University
    Inventors: Amit Solomon, Muriel Medard, Kenneth R. Duffy, Rabia Tugce Yazicigil Kirby, Vaibhav Bansal, Wei An
  • Patent number: 11853157
    Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 26, 2023
    Assignee: NXP B.V.
    Inventors: Arvind Kaushik, Aarul Jain, Nishant Jain
  • Patent number: 11855780
    Abstract: Various aspects related to ACK/NACK feedback for multi-TRP transmission scenarios are described. A base station, may send, to a UE, information indicating PDCCH monitoring occasions for each of a plurality of TRPs. In one aspect, the base station may send information indicating whether ACK/NACK feedback across the plurality of TRPs is allowed. The base station may send rules to the UE for performing ACK/NACK feedback bundling for providing feedback to the plurality of TRPs. The base station may also send information indicating a DAI definition for interpreting DAIs transmitted by the plurality of TRPs in corresponding PDCCH transmissions indicating whether the DAIs are independent or joint. The base station may receive a joint ACK/NACK feedback from the UE in a PUCCH based on the rules, or may receive multiple ACK/NACK feedback from the UE in a PUCCH for a first TRP independent from a second TRP.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: December 26, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaoxia Zhang, Jing Sun, Tamer Kadous
  • Patent number: 11831330
    Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: November 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Belkacem Mouhouche, Daniel Ansorregui Lobete, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11824558
    Abstract: An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: November 21, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 11816353
    Abstract: Technology is disclosed herein for managing parity data in non-volatile memory. As user data is programming into respective groups of non-volatile memory cells, the system accumulates parity data. The system may accumulate XOR parity based on successive bitwise XOR operations of user data. After programming is complete, the system performs a post-program read test of the data stored into each respective group of memory cells. The system re-calculates the parity data such that the parity data is no longer based on the user data that was stored in any group of memory cells for which the post-program read test failed. For example, the system will perform an additional bitwise XOR between the accumulated XOR parity data with the user data that was stored in the group of memory cells for which the post-program read test failed. The parity data is programmed to a group of memory cells.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: November 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Varun Sharma
  • Patent number: 11811424
    Abstract: Methods, systems, and devices for fixed weight codewords for ternary memory cells are described. A memory device may generate a codeword from a set of data bits and invert a portion of the codeword so that the codeword is associated with a target distribution of programmable states. After inverting the portion of the codeword, the memory device store the codeword in a set of ternary cells according to a coding scheme. The memory device may read the codeword from the set of ternary cells and select one or more reference voltages for the set of ternary cells based on the target distribution for the codeword and the states of the ternary cells.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Christophe Vincent Antoine Laurent, Riccardo Muzzetto
  • Patent number: 11797380
    Abstract: Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Jonathan S. Parry
  • Patent number: 11782642
    Abstract: Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply a plurality of analog weights to data using multiply-accumulate operations to generate an output. The device further comprises a digital weight storage unit configured to store digital weight references, wherein a digital weight reference corresponds to an analog weight of the plurality of analog weights. The device also comprises a device controller configured to program the plurality of analog weights to the CIM module based on the digital weight references and determine degradation of one or more analog weights. The digital weight references in the digital weight storage unit are populated with values from a host device. Degraded analog weights in the CIM module are replaced with corresponding digital weight references from the digital weight storage unit without reference to the host device.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Tung Thanh Hoang, Dejan Vucinic