Abstract: A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.

Abstract: In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.

Abstract: A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.

Abstract: A method for enhanced error protection using double-cyclic redundancy check (CRC) includes receiving a first packet, by a first physical layer (PHY). The first packet includes a source packet and a first CRC. The method also includes encrypting the first packet having the first CRC to generate an encrypted first packet. The method further includes appending a second CRC to the encrypted first packet to produce a second packet, and transmitting the second packet to a second PHY via a transmission line.

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

Abstract: An encoder receives a concatenated encoder input block d, splits d into an outer code input array a, and encodes a using outer codes to generate an outer code output array b. The encoder generates, from b, a concatenated code output array x using a layered polarization adjusted convolutional (LPAC) code. A decoder counts layers and carries out an inner decoding operation for a layered polarization adjusted convolutional (LPAC) code to generate an inner decoder decision {tilde over (b)}i from a concatenated decoder input array y and a cumulative decision feedback ({circumflex over (b)}1, {circumflex over (b)}2, . . . , {circumflex over (b)}i?1).

Abstract: A crossing frames encoding management method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: reading a tag swap information corresponding to a first physical group; encoding a first data; storing a first part of the encoded first data to at least one first physical unit corresponding to a first tag information in the first physical group; and storing a second part of the encoded first data to at least one second physical unit corresponding to a second tag information in the first physical group according to the tag swap information. The first tag information corresponds to a first crossing frames encoding group. The second tag information corresponds to a second crossing frames encoding group. The first crossing frames encoding group is different from the second crossing frames encoding group.

Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems are provided. In one aspect, a memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to: obtain a first reading output of target memory data in the memory using a first read voltage, and in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, provide the first read voltage to the memory. The memory is configured to: determine a second read voltage based on the first read voltage and generate a second reading output of the target memory data using the second read voltage.

Abstract: The inventive concept relates to method for encoding and decoding sparse codes and orthogonal sparse superposition codes. A sparse code encoding method which is to be performed by an encoding apparatus, according to an embodiment of the inventive concept may include selecting an index set that is a part of a code block by using an information bit, and mapping a codeword less than a preset size to the selected index set.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: In general, according to an embodiment, a storage device includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of pages, each of the pages including a data area of a first size and a redundant area of a second size smaller than the first size. The controller is configured to receive, from a host, a write command, receive, from the host, transfer data associated with the write command. The transfer data includes write data of the first size appended with a first error detection code for the write data. The controller is further configured to store the write data into the data area of one of the pages and the first error detection code into the redundant area of the one of the pages.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: A memory device includes a plurality of memory die blocks and a plurality of memory channels operably coupled to the plurality of memory die blocks and a memory controller configured to identify one or more memory die blocks as being invalid. The memory controller obtains a first matrix storing a mapping of memory channels to memory die blocks and creates a new mapping of memory channels to memory die blocks excluding the invalid memory die blocks. The new mapping is stored in a second matrix and one or more operations are performed on the memory die blocks based on the new mapping.

Abstract: Transferring data between memories may include reading data associated with a memory transfer transaction from a first memory, determining whether a bypass indication associated with the memory transfer transaction is asserted, and transferring the data from the first memory to a second memory. The transferring may include bypassing the first-processing if the bypass indication is asserted. The transferring may further include bypassing second-processing the data if the bypass indication is asserted. Following bypassing the second-processing, the data may be stored in the second memory.

Abstract: A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.

Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.

Abstract: Managing a temperature of a memory element of an information handling system, the method comprising: identifying a lower temperature boundary of the memory element; determining an initial temperature of the memory element; determining whether the initial temperature is less than the lower temperature boundary; in response to determining that the initial temperature is less than the lower temperature boundary: performing a series of repeated burst refresh operations at the memory element; after performing the series of repeated burst refreshes operations, determining an updated temperature of memory element; determining whether the updated temperature is less than the lower temperature boundary; and in response to determining that the updated temperature is greater than the lower temperature boundary, performing a normal boot of the memory element.

Abstract: A method and system for reliably forecasting storage disk failure. Specifically, the method and system disclosed herein entail predicting whether one or more storage disks may fail within a future time period. Further, the storage disk failure forecasts may rely on machine learning classification coupled with prediction reliability scoring.

Abstract: Systems and methods are disclosed for detecting shingled overwrite errors. When a read error is encountered when reading from shingled recording tracks, a processor may determine whether the read error is an error caused by shingled overwriting. The processor may determine whether the read error is caused by shingled overwriting by determining read signal quality of one or more sectors preceding the read error, such as based on a bit error count or bit error ratio (BER), and comparing the read signal quality to a threshold value. The processor may determine that the read error is caused by shingled overwriting when the read signal quality value is lower than the threshold.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.