Abstract: A method of manufacturing a layer sequence having a first and a second laterally confined structure comprises the steps of providing a first layer on a first surface portion of a substrate, which first layer is doped with dopant of a first type of conductivity, providing a second layer on a second surface portion of the substrate, which second layer is free of dopant of the first type of conductivity, forming a third layer on the first layer, which third layer is free of dopant of the first type of conductivity, and forming a fourth layer on the second layer, which forth layer is doped with dopant of the first type of conductivity. The first layer and the third layer are etched, thereby patterning the first and third layer to form the first laterally confined structure. The second layer and the forth layer are etched, thereby patterning the second and fourth layer to form the second laterally confined structure.

Abstract: A method including the steps of: modifying at least one part of a sapphire substrate by dry etching to thereby form any one of a dot shape, a stripe shape, a lattice shape, etc. as an island shape on the sapphire substrate; forming an AlN buffer layer on the sapphire substrate; and epitaxially growing a desired Group III nitride compound semiconductor vertically and laterally so that the AlN layer formed on a modified portion of the surface of the sapphire substrate is covered with the desirably Group III nitride compound semiconductor without any gap while the AlN layer formed on a non-modified portion of the surface of the sapphire substrate is used as a seed, wherein the AlN buffer layer is formed by means of reactive sputtering with Al as a target in an nitrogen atmosphere.

Abstract: A surface of a multicrystalline silicon substrate is etched with an alkaline aqueous solution in a condition so that a surface area-to-planar surface area ratio R is smaller than 1.1. A multiplicity of fine textures are formed over the irregularities by dry etching. This allows fine textures to be formed uniformly, and a solar cell with high efficiency can thus be produced.

Abstract: A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.

Abstract: A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.

Abstract: A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.

Abstract: Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.

Abstract: A method of forming semiconductor devices on a wafer is provided. An etch layer is formed over a wafer. A photoresist mask is formed over the etch layer. The photoresist mask is removed only around an outer edge of the wafer to expose the etch layer around the outer edge of the wafer. A deposition gas is provided comprising carbon and hydrogen containing species. A plasma is formed from the deposition gas. A polymer layer is deposited on the exposed etch layer around the outer edge of the wafer, wherein the polymer is formed from the plasma from the deposition gas. The etch layer is etched through the photoresist mask, while consuming the photoresist mask and the polymer deposited on the exposed etch layer around the outer edge of the wafer.

Abstract: An improvement in a copper damascene process is disclosed. The improvement comprises the step of projecting an electron beam on to a chemical mechanically polished material surface having copper filled etched trenches at a known angle of incidence with respect to the material surface for a known period of time, the electron beam having a beamwidth substantially covering the material surface and a known intensity.

Abstract: Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a photolithographic reticle including positioning the reticle in a first orientation on a reticle support in a processing chamber, wherein the reticle comprises a metal photomask layer formed on an optically transparent substrate, and a patterned resist material deposited on the metal photomask layer, etching the metal photomask layer in the first orientation, positioning the reticle in at least a second orientation, and etching the metal photomask layer in the at least second orientation.

Abstract: An improved method of manufacturing a capacitor on a semiconductor substrate is disclosed. A portion of an insulation film on a semiconductor substrate is etched to form a first opening in the insulation film. A passivation film is formed on the insulation film and within the first opening thereof. A portion of the passivation film on a bottom of the first opening is thinner than portions of the passivation film on the insulation film and on a sidewall of the first opening. The passivation film is etched to expose the bottom of the first opening.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method of fabricating an inkjet printhead chip for an inkjet printhead includes the step of depositing a first layer of a sacrificial material on a wafer substrate that incorporates drive circuitry. A deposition zone for a passive beam and a passive structure is formed with the first layer of sacrificial material. A metal layer is deposited on the first layer of sacrificial material. The metal layer is etched to define the passive beam and the passive structure. A second layer of a sacrificial material is deposited on the metal layer. A deposition zone for an active beam is formed on the second layer of sacrificial material. A metal layer is deposited on the second layer of sacrificial material. The metal layer is etched to define the active beam. The deposition zone is formed so that the metal layer makes electrical contact with the drive circuitry. A third layer of sacrificial material is deposited on the metal layer.

Abstract: A method of manufacturing a flash memory device includes the steps of forming a nitride film on an entire surface of a trench by means of an annealing process to prevent implanted ions for adjusting a threshold voltage from diffusing to a device isolation region, and forming a side wall oxide film on a surface of the nitride film. The nitride film plays a role of preventing ions implanted into a substrate for adjusting a threshold voltage from flowing into the side wall oxidation film.

Abstract: A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.

Abstract: In a mass flow sensor having a layered structure on the upper side of a silicon substrate (1), and having at least one heating element (8) patterned out of a conductive layer in the layered structure, thermal insulation between the heating element (8) and the silicon substrate (1) is achieved by way of a silicon dioxide block (5) which is produced beneath the heating element (8) either in the layered structure on the silicon substrate (1) or in the upper side of the silicon substrate (1). As a result, the sensor can be manufactured by surface micromechanics, i.e. without wafer back-side processes.

Abstract: A method for forming a circuit pattern includes at least a step (a) of subjecting a non-conductor to electroless copper plating to form a copper film and a step (b) of etching the copper film so as to form a circuit pattern. As a catalyst for the electroless copper plating, a silver colloidal solution is used containing as essential components at least the following: (I) silver colloidal particles; (II) one or more of ions of metal having an electric potential which can reduce silver ions to metal silver in the solution and/or ions which result from oxidation of the ion at the time of reduction of the silver ions; and (III) one or more of hydroxycarboxylate, condensed phosphate and/or amine carboxylate ions. The silver colloidal particles (I) are produced by the ion (II) of the metal having an electric potential which can reduce silver ions to metal silver. The circuit pattern may be formed on a printed wiring board.

Abstract: A multilayer piezoelectric element 2 comprising an element body 10 wherein piezoelectric layers 8 and internal electrode layers 4 and 6 are alternately stacked. The piezoelectric layer 8 is composed of a piezoelectric ceramic. The piezoelectric ceramic includes a compound oxide having a perovskite structure. The compound oxide contains at least lead, zirconium and titanium. The method of producing the piezoelectric element includes the steps of producing a piezoelectric layer ceramic green sheet, forming a pre-fired element body by alternately stacking the produced piezoelectric ceramic green sheets and internal electrode layer precursor layers, and forming said element body 10 by performing main firing on the pre-fired element body at a temperature of 1100° C. or lower.

Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).