Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.

Abstract: There is provided a magnetic memory device which has a small switching current for a writing line and which has a small variation therein. A method for producing such a magnetic memory device includes: forming a magnetoresistive effect element; forming a first insulating film so as to cover the magnetoresistive effect element; forming a coating film so as to cover the first insulating film; exposing a top face of the magnetoresistive effect element; forming an upper writing line on the magnetoresistive effect element; exposing the first insulating film on a side portion of the magnetoresistive effect element by removing a part or all of the coating film; and forming a yoke structural member so as to cover at least a side portion of the upper writing line and so as to contact the exposed first insulating film on the side portion of the magnetoresistive effect element.

Abstract: A sub-micron structure is fabricated in a transparent dielectric material by focusing femtosecond laser pulses into the dielectric to create a highly tapered modified zone with modified etch properties. The dielectric material is then selectively etched into the modified zone from the direction of the narrow end of the tapered zone so that as the selective etching proceeds longitudinally into the modified zone, the progressively increasing width of the modified zone compensates for lateral etching occurring closer to the narrow end so as to produce steep-walled holes. The unetched portion of the modified zone produced by translating the laser beam close to and parallel to the bottom surface of the dielectric can serve as an optical waveguide to collect light from or deliver light to the etched channel which can contain various biological, optical, or chemical materials for sensing applications.

Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used.

Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a substrate. A polysilicon layer is formed overlying the dielectric layer. A patterned masking layer with an opening is formed overlying the polysilicon layer. Through the opening, the polysilicon layer is oxidized to form a first silicon oxide layer at the bottom of the opening. Thereafter the masking layer is removed and the polysilicon layer is exposed. The exposed polysilicon layer is then etched through using the first silicon oxide layer as a mask to form MOS floating gates. The first silicon oxide layer is then removed. A second conductor layer is then deposited overlying the MOS floating gates for forming control gates.

Abstract: After etching a Si-containing low permittivity insulating film with chlorine based gas, the etched wafer is subjected to an etching aftertreatment process comprising introducing oxygen gas to a vacuum processing chamber with a pressure as low as 0.2 Pa to 1 Pa and a flow rate as low as 5 cc to 20 cc/min, generating plasma within the chamber, heating the wafer 2 being subjected to aftertreatment between 50° C. and 200° C., applying a wafer bias power within the range of 50 W to 200 W, and exposing the wafer to the generated plasma, thereby simultaneously removing the photoresist components, the antireflection film components and the halogen components.

Abstract: In a method for photo-electrochemical etching of a semiconductor sample, the semiconductor sample is brought in contact with an electrolyte liquid. The contact area formed thereby is illuminated through the electrolyte liquid with UV light. The photo-current created by UV light irradiation at the contact area is measured. To increase the etching quality, a jet of fresh electrolyte liquid is repeatedly applied to the contact area. A device for carrying out the method includes a container to be filled with an electrolyte liquid, a UV source for illuminating the semiconductor sample with UV light through the electrolyte liquid, and a measuring instrument for measuring the photo-current created during UV light irradiation of the contact area. Further provided are an inlet for supplying fresh electrolyte liquid, directed towards the semiconductor sample, and a device attached to the inlet for repeated production of electrolyte fluid jets, directed towards the semiconductor sample.

Abstract: Non-chromate solutions for treating and/or etching metals, particularly, aluminum, aluminum alloys, steel and titanium, and method of applying same wherein the solutions include either a titanate or titanium dioxide as a “drop-in replacement” for a chromium-containing compound in a metal surface etching solution that otherwise would contain chromium.

Abstract: Disclosed is a method for forming a conductor on a dielectric. The method commences with the deposition of a conductive thickfilm on the dielectric, followed by a “subsintering” of the conductive thickfilm. Either before or after the subsintering, the conductive thickfilm is patterned to define at least one conductor. After subsintering, the conductive thickfilm is etched to expose the conductor(s), and the conductor(s) are then fired. A brief chemical etch may be used after the final firing step if improved wire-bondability is required.

Abstract: A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

Abstract: A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (Vf) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and sub-surface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.

Abstract: An aqueous polishing composition comprises a corrosion inhibitor for limiting removal of an interconnect metal with an acidic pH. The composition includes an organic-containing ammonium salt formed with R1, R2, R3 and R4 are radicals, R1 has a carbon chain length of 2 to 15 carbon atoms. The organic-containing ammonium salt has a concentration that accelerates TEOS removal and decreases removal of at least one coating selected from the group consisting of SiC, SiCN, Si3N4 and SiCO.

Abstract: A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.

Abstract: A method for forming a structure including multiple wire-layers, the method including providing a plurality of first wires (in a layer) on an underlying layer; providing a liner insulating film on the underlying layer so as to coat the first wires and have concave portions respectively between the mutually adjacent first wires; providing a buried insulating film in the concave portions and on the liner insulating film; providing a cap insulating film so as to coat the buried insulating film; and providing a second wire layer on or above the cap insulating film. The buried insulating film is made of an insulating material having a dielectric constant, which is lower than that of the liner insulating film and the cap insulating film.

Abstract: In one embodiment, a plurality of thickfilm dielectric layers are printed on a substrate, with each successive layer being printed over a previous layer, and with each layer having sloped walls. After printing a first subset of the plurality of thickfilm dielectric layers, a first conductive thickfilm is printed over at least the walls of the first subset of dielectric layers. Then, after printing a second subset of the plurality of thickfilm dielectric layers, a second conductive thickfilm is printed over the second subset of dielectric layers (with the first and second conductive thickfilms being electrically coupled).

Abstract: A technique is provided that may be used to improve optical endpoint detection in a plasma etch process. A semiconductor structure is manufactured that includes at least one electrical device. The technique is adapted for forming a signal layer on or in a wafer, wherein the signal layer comprises a chemical element that causes a characteristic optical emission when coming into contact with an etch plasma. The chemical element does not have a primary influence on the electrical properties of the electrical device. The signal layer is for use in a plasma etch process to detect a plasma etch endpoint if the characteristic optical emission is detected. The signal layer may be patterned and may be incorporated into a stop layer.

Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Abstract: Non-chromate solutions for treating and/or etching metals, particularly, aluminum, aluminum alloys, steel and titanium, and method of applying same wherein the solutions include either a titanate or titanium dioxide as a “drop-in replacement” for a chromium-containing compound in a metal surface etching solution that otherwise would contain chromium.

Abstract: A method for etching a silicon on insulator (SOI) substrate includes opening a hardmask layer formed on an SOI layer, and etching through the SOI layer, a buried insulator layer underneath the SOI layer, and a bulk silicon layer beneath the buried insulator layer using a single etch step.