Abstract: The invention relates to a process for chemically mechanically polishing and grinding wafers. The CMP slurry that is used for grinding is analyzed using slurry atomic absorption spectroscopy. This allows rapid and sensitive analysis of the slurry constituents, in particular of interfering ions. The process can be automated and makes it possible to process wafers with a constant quality. Furthermore, rapid fault analysis or optimization of the process parameters used during the grinding is possible.

Abstract: A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical transistors in an array area separated by isolation trenches residing in both array and support areas. A top oxide nitride (TON) liner is deposited over array and support areas so as to directly contact the fill in the isolation trenches. An array top oxide (ATO) is then deposited directly over the TON liner such that during subsequent processing, the TON protects the isolation trench oxide from any divot opening etches while maintaining the isolation trench oxide height fixed during the ATO process. In further processing the intermediate structure, ATO and TON are removed from the support area only, leaving remaining portions of both ATO and TON only in the array area, such that the TON liner separates the ATO from the isolation trench fill.

Abstract: A method for reducing the dimension of a patterned organic photoresist area by reducing the pressure of a reactive environment surrounding the patterned photoresist to cause outgasing. The outgased materials CxHyOz are then decomposed in the reactive environment leaving the outgased photoresist porous. The environment surrounding the patterned photoresist is then increased to atmospheric pressure, which compresses or shrinks the porous photoresist. Photoresist lines having a dimension as small as about 0.085 ?m can be obtained.

Abstract: Methods for protecting the sidewall of a metal interconnect component using Physical Vapor Deposition (PVD) processes and using a single barrier metal material. After forming the metal interconnect component, a single barrier metal is deposited on its sidewall using PVD. A subsequent anisotropic etching of the barrier metal removes the barrier metal from the horizontal surface except for some that still remains on the top surface of the metal interconnect layer. A dielectric layer is then formed over the metal interconnect component and the barrier metal. The unlanded via is etched through the dielectric layer to the metal interconnect component, and then filled with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.

Abstract: Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulated, for that body, on an area of another pattern density for each of the CMP processes.

Abstract: A method for manufacturing a semiconductor device having a movable unit includes a step of forming an SOI substrate that includes a semiconductor substrate, an insulating layer, and a semiconductor layer such that the insulating layer is located between the semiconductor layer and the semiconductor substrate. The method further includes a step of dry etching the semiconductor layer to form a trench with a charge prevented from building up on a surface of the insulating layer that is exposed at a bottom of the trench during the dry etching. The method further includes a step of dry etching a sidewall defining the trench at a portion adjacent to the bottom of the trench to form the movable unit. The later dry etching is performed with a charge building up on the surface of the insulating layer such that etching ions strike to etch the portion of the sidewall.

Abstract: A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.

Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.

Abstract: The present invention teaches a method and apparatus for removing sacrificial materials in fabrications of microstructures using one or more selected spontaneous vapor phase etchants. The selected etchant is fed into an etch chamber containing the microstructure during each feeding cycle of a sequence of feeding cycles until the sacrificial material of the microstructure is exhausted through the chemical reaction between the etchant and the sacrificial material. Specifically, during a first feeding cycle, a first amount of selected spontaneous vapor phase etchant is fed into the etch chamber. At a second feeding cycle, a second amount of the etchant is fed into the etch chamber. The first amount and the second amount of the selected etchant may or may not be the same. The time duration of the feeding cycles are individually adjustable.

Abstract: An improved CMP controller allows the calculation of the polish time required for removing a patterned layer stack to a desired final thickness, wherein the initial layer thickness of each layer contained in the layer stack is employed. Moreover, a topography factor characterizing the surface structure of the layer stack and a selectivity characterizing the ratio of removal rates between adjacent material layers are used. Furthermore, a state variable of the controller represented by the removal rate of one of the layers may periodically be updated on the basis of the previously calculated polish time and a measurement value of the finally obtained layer thickness. The improved controller is particularly advantageous in the CMP process for STI isolation structures, in which the final thickness of a CMP stop layer, having a significantly reduced removal rate compared to the overlying dielectric layer, has to be precisely controlled.

Abstract: In manufacturing a semiconductor device, a part of an element is formed on the surface of a substrate, and at least a periphery of the substrate is polished using a polishing member stretched around the periphery of the substrate so that a polishing face of the polishing member is slid on a polishing target surface of the periphery.

Abstract: A method for forming a photoresist pattern with minimally reduced transformations through the use of ArF photolithography, including the steps of: forming an organic anti-reflective coating layer on a an etch-target layer already formed on a substrate; coating a photoresist for ArF on the organic anti-reflective coating layer; exposing the photoresist with ArF laser; forming a first photoresist pattern by developing the photoresist, wherein portions of the organic anti-reflective coating layer are revealed; etching the organic anti-reflective coating layer with the first photoresist pattern as an etch mask and forming a second photoresist pattern by attaching polymer to the first photoresist pattern, wherein the polymer is generated during etching the organic anti-reflection coating layer with an etchant including O2 plasma; and etching the etch-target layer by using the second photoresist pattern as an etch mask.

Abstract: A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.