Abstract: Energy consumption is reduced within an Internet of Things (IoT) device, without degrading operating performance of the corresponding internal circuitry. A first internal supply voltage (VDDa) used to supply the internal circuitry is reduced from a VDD supply voltage to a lower voltage during an idle state, thereby reducing leakage currents in the internal circuitry. The first internal supply voltage (VDDa) may be reduced to a voltage that is one threshold voltage (Vtp) lower than the VDD supply voltage. A second internal supply voltage (VSSa) used to supply the internal circuitry is increased from the VSS supply voltage to a voltage higher than the VSS supply voltage during the idle state, thereby further reducing leakage currents in the internal circuitry. The second internal supply voltage (VSSa) may be increased to a voltage that is one threshold voltage (Vtn) higher than the VSS supply voltage.

Abstract: A real-time workload scheduling heuristic assigns tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators.

Abstract: A method of tuning performance of a data storage system includes calculating an estimate of parallel fraction and speedup characteristic for a data storage application executed by the data storage system. The estimate is calculated using linear regression of values (1/N, 1/XN) that are generated from trial runs of the data storage application processing a workload using respective different numbers N of CPU cores to obtain corresponding performance values XN. The method further includes configuring the data storage system to execute the data storage application using a number of CPU cores based on the estimate of parallel fraction and speedup characteristic.

Abstract: The electronic apparatus of the present invention includes: a power source control unit allocated to each of a plurality of external interfaces and configured to control supply or shutoff of a current for an external device and to output whether or not an overcurrent is detected as an overcurrent detection signal; a control unit configured to control supply or shutoff of a current; a logical product circuit that outputs a logical product of the overcurrent detection signals as an external interrupt signal; and an interface control unit configured to, in a case where the overcurrent detection signals is asserted, output external interface information specifying an external interface at which the overcurrent has occurred, and the control unit, in a case where the external interrupt signal is asserted, controls to the power source control unit at which the overcurrent has been detected so as to shut off supply of power.

Abstract: An information processing apparatus includes: an imaging unit having an image sensor to detect a plurality of pieces of pixel information, the imaging unit being configured to generate an image made up of the plurality of pieces of pixel information detected by the image sensor; an image processor to detect whether a user is present or not in a predetermined detection range, based on an image made up of a plurality of pieces of pixel information detected by the image sensor; and an operation control unit to, when the image processor detects the user in the predetermined range, cancel a standby state where a part of the system functions stops. In the standby state, the imaging unit increases at least one of resolution and a frame rate in a stepwise manner to detect the plurality of pieces of pixel information.

Abstract: A circuit for identifying a power supply may include a voltage divider to divide an identification voltage from the power supply. The output of the voltage divider is electrically coupled to an adapter identification pin of a controller to identify the power supply.

Abstract: An apparatus and method are provided for partially discharging a power supply, the apparatus comprising a power supply adapted to supply power to processing circuitry to perform a processing operation and discharge circuitry adapted to partially discharge the power supply after the processing operation is complete.

Abstract: Some embodiments include a Power Over Ethernet (POE) monitor system powered by a POE signal. Some embodiments include a snap on POE module that is coupled to a monitor of the POE monitor system via a single connector without cabling. Some embodiments include creating and implementing a POE profile that specifies how power is utilized when the POE touchscreen system is powered by a POE-DC signal (e.g., reducing one or more of: a number of active USB ports, active audio devices, or touchscreen brightness to a %.) Some embodiments include detecting a power loss, and using one or more POE super capacitors to provide power for completion of critical functions that enable a graceful shut down. One or more of the POE super capacitors may be located in the snap on POE module, or in a main unit of the monitor.

Abstract: Circuits, methods, and apparatus that may determine one or more characteristics relating to a mains power supply received by a computer system, and may then determine a maximum amount of power that may be drawn by the computer system given the determined characteristics. An example may provide a computer system having a power supply circuit that may include a detection circuit to receive a mains power supply and to detect a characteristic of the mains power supply. In response to the detected characteristic, the detection circuit may provide an output to a circuit in the computer system that sets a limit on a current that may be drawn by the circuit. In this example, the characteristic may be an RMS value of the mains power supply waveform, a location of where the mains power supply is being received, a quality of the mains power supply, or other characteristic.

Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.

Abstract: A computing resource service provider provides computing resources to customers, for example, computer system instances supported by server computer systems. These computer system instances may include logical volumes to support execution of the computer system instance. In addition, these instances may be terminated from time to time for various reasons. A stop signal transmitted to computing resource supporting a particular computer system instance may indicate that the particular computer system instance is to be terminated. In response to termination, the particular computer system instance may operate in accordance to a particular behavior.

Abstract: The power consumption of an analog arithmetic circuit is reduced. The analog arithmetic circuit includes a plurality of first circuits. An output terminal of the k-th (k is a natural number) first circuit is connected to an input terminal of the k+1-th first circuit. Each of the first circuits includes a memory circuit which holds an analog signal, a second circuit which performs arithmetic processing using the analog signal, a switch which controls power supply to the second circuit, and a controller. The conduction state of the switch included in the k-th first circuit is controlled by the controller included in the k+1-th first circuit. The arithmetic processing performed by the second circuit included in the k+1-th first circuit is started by the controller included in the k+1-th first circuit.

Abstract: A false-touch-wakeup prevention apparatus touch sensing, proximity sensing, NAND logic, AND logic and application processing devices. First, second input ends and output end of the AND logic are coupled to the touch sensing device, an output end of the NAND logic device, and the application processing device, respectively; first and second input ends of the NAND logic are coupled to the proximity sensing device, and the application processing device, respectively; when an initial state of the application processing is standby, the second input end of the NAND logic device inputs a first input value; when the initial state of the application processing is wakeup, the second input end of the NAND logic device inputs a second input value different from the first input value.

Abstract: Techniques for power source management in an information handling system (IHS) include detecting connection of multiple power sources to the IHS through respective DC adapters, obtaining data indicating the capabilities of each power source, obtaining data indicating a system load for the IHS, and generating, based on the obtained data, a load management plan specifying a target combined input power amount for power supplied by the multiple power sources and respective amounts of electrical power to be supplied by a single selected power source or by multiple selected power sources. The techniques also include combining the power supplied by each of the selected power sources into a combined input power and supplying the combined input power to the IHS. Prior to the combining, the voltage of the power supplied by a power source may be stepped up or down to a common voltage, or a power source may be de-rated.

Abstract: Medical device data manager configuration methods and systems including a medical device, a smart mobile device including a camera, a processor, a memory communicatively coupled to the processor, and machine readable instructions stored in the memory that may cause a system to perform at least the following when executed by the processor: use the camera of the smart mobile device to capture an image of the medical device; apply an identification algorithm to the image of the medical device; identify the medical device as an identified medical device based on the image of the medical device and the identification algorithm; and automatically configure a software application tool on the smart mobile device to retrieve data associated with one or more requirements of the identified medical device.

Abstract: Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.

Abstract: A method is provided in one example embodiment and includes storing secure boot variables in a baseboard management controller; and sending the secure boot variables to a basic input/output system (BIOS) during a power on self-test, where the BIOS utilizes the secure boot variables during runtime to authenticate drivers and an operating system loader execution. In particular embodiments, the secure boot variables may be included in a white list, a black list, or a key list and, further, stored in erasable programmable read only memory.

Abstract: A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in another architectural mode of the plurality of architectural modes, wherein the another architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the another architectural mode in place of the one architectural mode restricting use of the one architectural mode.

Abstract: A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in other architectural mode of the plurality of architectural modes, wherein the other architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the other architectural mode in place of the one architectural mode restricting use of the one architectural mode.

Abstract: An Ethernet power sourcing equipment (PSE), and a method and an apparatus for power over Ethernet (PoE), where the Ethernet PSE includes a PSE chip, a master control processor, a power supplying port, and a preprocessor. The preprocessor is configured to determine whether the master control processor starts upon power-on, control the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD) when the master control processor starts upon power-on, and control, according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD. Hence, the Ethernet PSE has abundant management functions and can quickly power on a PD.