Patents Examined by Eric Chang
  • Patent number: 10437318
    Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
    Type: Grant
    Filed: January 2, 2016
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
  • Patent number: 10437319
    Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
    Type: Grant
    Filed: January 2, 2016
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
  • Patent number: 10430202
    Abstract: Techniques for detecting an early boot error are provided. In one aspect, a host processor may transition to a first phase of an early boot process. The early boot process may occur before the host processor initializes a primary link between the host processor and a management controller. The host processor may then update a dual purpose boot register to store an early boot phase identifier corresponding to the first phase and an early boot status identifier corresponding to the first phase.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 1, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Suhas Shivanna, Srinivasan Varadarajan Sahasranamam, Nagaraj S Salotagi
  • Patent number: 10423346
    Abstract: An apparatus for processing data 2 contains multiple power domains which may be in a non-retaining power state or a retaining power state. If a power domain is in a non-retaining power state in which it is not able to retain a copy of a stored parameter value and it is switched into a retaining power state in which it requires a copy of that parameter value, then it fetches the parameter value from a store within another power domain. One of the power domains contains a master copy of the parameter value to which writes changing in the parameter value are made. At least one of the other power domains fetches a copy of the parameter value if required from a power domain other than the power domain containing the master copy.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 24, 2019
    Assignee: ARM Limited
    Inventor: Arthur Brian Laughton
  • Patent number: 10423436
    Abstract: Techniques for managing energy use of a computing deployment are provided. In one embodiment, a computer system can establish a performance model for one or more components of the computing deployment, where the performance model models a relationship between one or more tunable parameters of the one or more components and an end-to-end performance metric, and where the end-to-end performance metric reflects user-observable performance of a service provided by the computing deployment. The computer system can further execute an algorithm to determine values for the one or more tunable parameters that minimize power consumption of the one or more components, where the algorithm guarantees that the determined values will not cause the end-to-end performance metric, as calculated by the performance model, to cross a predefined threshold. The computer system can then enforce the determined values by applying changes to the one or more components.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: September 24, 2019
    Assignee: VMware Inc.
    Inventors: Xing Fu, Tariq Magdon-Ismail
  • Patent number: 10379558
    Abstract: Embodiments are described for dynamically responding to demand for server computing resources. The embodiments can monitor performance of each of multiple computing systems in a data center, identify a particular computing system of the multiple computing systems for allocation of additional computing power, determine availability of an additional power supply to allocate to the identified computing system, determine availability of a capacity on a power distribution line connected to the particular computing system to provide the additional power supply to the particular computing system, and allocate the additional computing power to the identified computing system as a function of the determined availability of the additional power supply and the determined availability of the capacity on the power distribution line.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: August 13, 2019
    Assignee: Facebook, Inc.
    Inventors: Xiaojun Liang, Yusuf Abdulghani, Ming Ni, Hongzhong Jia, Jason Taylor
  • Patent number: 10379586
    Abstract: One embodiment provides a method, including: executing, using at least one processor, computer readable program code to: identify a plurality of possibilities at the disposal of a data center for changing its energy demand in its role as a consumer of energy, wherein each of the possibilities is associated with: a time interval during which change in energy consumption of the data center is to take place; and an amount of energy to be drawn, during the time interval, by the data center from an electric provider through a connection to a power grid; wherein the plurality of possibilities are different from each other; proactively determine, based on the identified plurality of possibilities, the ability of the data center to change its energy consumption, thereby changing the amount of energy drawn by the data center from the energy provider; and communicate, to a remote device that is in direct communication with an energy supplier, data indicating the ability of the data center to change its energy consumpti
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ranjini Bangalore Guruprasad, Shivkumar Kalyanaraman, Dilip Krishnaswamy, Prakash Murali
  • Patent number: 10360043
    Abstract: Device drivers are provided from virtual media. System resources trap input/output data associated with the device drivers. Memory is allocated for the virtual media and populated with the device drivers using the input/output data. As an operating system installs, the virtual media is readable and is accessed for the device drivers.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: July 23, 2019
    Assignee: Dell Products, LP
    Inventors: Allen C. Wynn, Chris E. Pepper, Justin W. Johnson
  • Patent number: 10353451
    Abstract: In a system using a device not adapted to a single wire bus, a semiconductor device includes an external terminal to be coupled to a power source terminal of an external device, a port that supplies a power source voltage for the external device to the external terminal, a power manager that controls an output of the port, and a CPU that controls an operation of the power manager.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: July 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Ishikawa, Yoshiaki Daimon, Norihiko Ishizaki, Yuichi Iwaya
  • Patent number: 10338936
    Abstract: A method may include associating, with a timer-B, a second application in a terminal device; setting the terminal device in a standby mode; and executing the second application when a processor in the terminal device wakes up after the timer-B measures a second amount of elapsed time. The timer-B may not initiate wake-up of the processor. The method may further include determining whether the second application is associated with the timer-B or a timer-A when the terminal device receives a command of setting the terminal device in the standby mode; and when the second application is determined as being associated with the timer-A, unassociating the second application with the timer-A. The timer-A may initiate wake-up of the processor when the timer-A measures another second amount of elapsed time while the terminal device is the standby mode. A timer associated with a first application may initiate wakeup of the processor.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 2, 2019
    Assignee: Sony Corporation
    Inventor: Koichi Kato
  • Patent number: 10324732
    Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 18, 2019
    Assignee: ATI TECHNOLOGIES ULC.
    Inventors: Behrooz Karimian-Kakolaki, Darlington C. Opara
  • Patent number: 10318309
    Abstract: An embedded system has a data processing apparatus that executes program code and a sequencing controller for switching components of the embedded system on and off, the data processing apparatus and the sequencing controller connected to one another via an individual control signal line, and the sequencing controller arranged to either switch off or restart the embedded system on the basis of a temporal profile of a control signal received via the control signal line.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 11, 2019
    Assignee: Fujitsu Technology Solutions Intellectual Property GmbH
    Inventor: Timo Bruderek
  • Patent number: 10296075
    Abstract: In an embodiment, an apparatus includes an input circuit coupled to a first power supply with a first voltage level, a power circuit coupled to a second power supply with a second voltage level, and an output driver. The input circuit may receive an input signal, and generate an inverted signal dependent upon the input signal. The power circuit may generate a power signal in response to first values of the input and the inverted signals, wherein a voltage level of the power signal may be dependent upon the second voltage level. The power circuit may also generate a third voltage level on the power signal in response to second values of the input and the inverted signals. The output driver may generate an output signal dependent upon the input signal. The output signal may transition between the voltage level of the power signal and the ground reference level.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 21, 2019
    Assignee: Apple Inc.
    Inventors: Zhao Wang, Miles G. Canada
  • Patent number: 10263876
    Abstract: Disclosed are various embodiments for a timeout management application. Latency data for executing services is obtained. The used service capacity is calculated. If the service capacity is outside of a predefined range, the timeout of a selected service is reconfigured.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 16, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Kaloyan K. Kraev
  • Patent number: 10228830
    Abstract: Embodiments of the present disclosure disclose a method for starting an application program, a terminal and a non-transitory computer readable storage medium, relating to the field of communications, for providing a method capable of quickly starting an application program without starting each functional module of the terminal. In the embodiments of the present disclosure, after a minimum system of the terminal is started, a preset quick start interface is loaded through a display module of the minimum system, wherein the quick start interface at least comprises a plurality of virtual hotkeys for identifying application programs to be started; according to an operation on a virtual hotkey corresponding to starting of an application program, a virtual system executes an operation of starting the application program, wherein the virtual system and a host system of the terminal share physical resources of the terminal.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 12, 2019
    Assignees: HISENSE ELECTRIC CO., LTD., HISENSE USA CORPORATION, HISENSE INTERNATIONAL CO., LTD.
    Inventors: Guilin Hou, Fei Huang
  • Patent number: 10222848
    Abstract: The power consumption of an analog arithmetic circuit is reduced. The analog arithmetic circuit includes a plurality of first circuits. An output terminal of the k-th (k is a natural number) first circuit is connected to an input terminal of the k+1-th first circuit. Each of the first circuits includes a memory circuit which holds an analog signal, a second circuit which performs arithmetic processing using the analog signal, a switch which controls power supply to the second circuit, and a controller. The conduction state of the switch included in the k-th first circuit is controlled by the controller included in the k+1-th first circuit. The arithmetic processing performed by the second circuit included in the k+1-th first circuit is started by the controller included in the k+1-th first circuit.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Shunpei Yamazaki
  • Patent number: 10223531
    Abstract: A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 5, 2019
    Assignee: Google LLC
    Inventors: Marius Schilder, Timothy Chen, Scott Johnson, Harrison Pham, Derek Martin
  • Patent number: 10216220
    Abstract: A first request signal that indicates a request for a time maintained by a clock implemented in first circuitry is sent from second circuitry. The first circuitry utilizes a first clock signal derived from a first oscillator and the second circuitry utilizes a second clock signal derived from a second oscillator. The first circuitry adjusts a first time value from the clock to compensate for a first latency or jitter caused by converting the first request signal to a second request signal synchronized to the first clock. The second circuitry further adjusts the adjusted first time value to generate a second time value that compensates for i) a second latency between sending the first request signal and receiving the adjusted first time value, and ii) a third latency or jitter caused by synchronizing the adjusted first time value to the second clock.
    Type: Grant
    Filed: January 15, 2017
    Date of Patent: February 26, 2019
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Tal Mizrahi
  • Patent number: 10209763
    Abstract: A method is described and in one embodiment includes, for each of a plurality of outgoing ports of a first network element: collecting data comprising a number of packets arriving the outgoing port and an amount of power consumed by the outgoing port for a first time interval; calculating a packet per watt (“P/W”) metric for the port for the first time interval, wherein the P/W metric comprises the number of packets coming into the port divided by the amount of power consumed by the port during the first time interval; repeating the collecting and calculating for a number of successive time intervals; calculating a mean P/W metric for a time period comprising the first time interval and the successive time intervals; and calculating a variance for the time period comprising the first time interval and the successive time intervals. The method further includes redirecting traffic received at the network element to the outgoing port having the lowest variance.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 19, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Anand V. Akella, Praveen Parthasarathy Iyengar, Rajendra Kumar Thirumurthi, Samar Sharma, Krishna Bharadwaj Dharwada, Vivek Purushotham
  • Patent number: 10191782
    Abstract: In one aspect a disclosed method may include determining, by an information handling system, a future predicted system time that an unattended task is to be executed on the information handling system. The future predicted system time is based at least in part on first usage parameters for a user indicating first periods of usage activity, second periods of inactivity associated with the information handling system recorded during a first duration, and critical system parameters relevant to the present state of the information handling system. The method may also include ensuring that system resources of the information handling system are available for the unattended task to be able to complete. In response to the arrival of the future predicted system time, the unattended task is executed.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: January 29, 2019
    Assignee: Dell Products, LP
    Inventors: Nicholas D. Grobelny, Abeye Teshome