Abstract: Methods, systems, and computer-readable storage media for receiving a configuration descriptor from configuration descriptor repository, the configuration descriptor declaring a configuration task, and providing an order of invoking two or more application programming interfaces (APIs) to respective components of the enterprise-side landscape to execute the configuration task, processing the configuration descriptor by a configuration executor of an integration services platform to automatically execute at least a portion of the configuration task by invoking the two or more APIs in the order, a response of a first API being provided as a request to a second API, and selectively indicating one of success and failure of the configuration task based on at least one response of the two or more APIs.

Abstract: A method for power control includes determining a load power of a load coupled to an output of an isolated AC/DC power supply. The method also includes, when the determined load power is less than a first threshold load power, providing the load power to the load from an interim power source.

Abstract: A digital integrated circuit comprising may include a digital sensor circuit that converts binary bit patterns of wires in a sub-circuit over a given time into a single integer value that represents the total activity of a sub-circuit, and a digital data processing circuit that receives multiple activity integer values from multiple digital sensors in multiple sub-circuits and logically combines the values or uses a lookup table to output a single integer value that represents the total activity of a larger sub-circuit.

Abstract: A processor memory mapped boot system includes a processing system having a processor memory subsystem, and a memory system having at least one memory device. A Basic Input/Output System (BIOS) engine is coupled to the processing system and the memory system, and is configured to begin boot operations and detect a boot memory mode setting for the processor memory subsystem. The BIOS engine configures a memory space that includes the at least one memory device and the processor memory subsystem. In response to detecting the boot memory mode setting, the BIOS engine will configured the processor memory subsystem to provide a first memory region of the memory space. The BIOS engine will then complete boot operations utilizing the processor memory subsystem providing the first memory region of the memory space.

Abstract: A method of controlling a hard disk and an electronic device, comprising: determining a number of power cycles that have been completed by the hard disk at a time point within a predetermined period of time, a power cycle including a total duration of the hard disk in a spin-on mode and an immediately neighboring spin-off mode; and in response to the number of power cycles that have been completed being below an upper limit number for the power cycles of the hard disk in the predetermined period of time, determining remaining time of the predetermined period of time starting from the time point, and determining, based on the remaining time, the number of power cycles that have been completed, and the upper limit number, a threshold idle duration for controlling the hard disk to enter the spin-off mode.

Abstract: Booting a virtual machine instance using remote direct memory access is provided. In response to beginning to receive pages of a predetermined set of pages corresponding to a requested image of a virtual machine from an image provider server, a boot process of an instance of the virtual machine is commenced while the received pages are written directly into a random-access memory (RAM) disk. The received pages are read from the RAM disk during the boot process of the instance of the virtual machine until transfer of the predetermined set of pages corresponding to the requested image is complete. The predetermined set of pages corresponding to the requested image are written to a local hard disk drive from the memory releasing memory usage. In response to completing the boot process, a RAM image is switched to a local hard disk drive image.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine respective priority levels for one or more boot time events, determine an amount of execution time for the one or more boot time events, and automatically adjust a timer based on the amount of execution time and the priority levels for the one or more boot time events. Other embodiments are disclosed and claimed.

Abstract: A computing device includes a processor having a plurality of cores, a core translation component, and a core assignment component. The core translation component provides a set of registers, one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transferred to a respective core based on the core indices.

Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.

Abstract: A method, apparatus and computer program are provided for allocating power amount a plurality of computing devices. The method includes determining a current power capping amount for each of a plurality of computing devices and obtaining a current power usage of each computing device. The method further includes determining, for each computing device, an updated power capping amount based on whether or not the current power usage of the computing device has reached the current power capping amount of the computing device during a current period of time. The updated power capping amount is allocated to the respective computing devices, and a power supply is caused to deliver power to each computing device in an amount up to the updated power capping amount that has been allocated to the respective computing device.

Abstract: Techniques relating to communicating system events in universal serial bus (USB) power delivery (PD) devices are described. In an example, a USB PD controller receives a notification of a system event in a first device associated with the USB PD controller, the system event being based on one of a change in machine state of the first device and occurrence of a user interaction event in the first device. A PD protocol based message, indicative of the system event in the first device, is generated. The PD protocol based message provides for activation of a predefined profile setting in a second device, wherein the second device is to interface with the first device through the USB PD controller.

Abstract: A method for creating devices facilitating secure data transmission, storage and key management. At least two devices are each comprised of at least part of a physically unclonable function unit originally shared by the at least two devices on a single, monolithic original integrated circuit. The process includes physically segmenting the shared physically unclonable function unit between the at least two devices. The at least two devices which share the single, monolithic integrated circuit are physically separated into individual device units.

Abstract: Network hardware of a computing device receives a network packet over a network to which the network hardware is connected. The network hardware determines that the network packet includes a power-cycling command. The network hardware, in response to determining that the network packet includes the power-cycling command, triggers a physical line between the network hardware and a power supply of the computing device. The power supply is connected to a power source and currently provides power from the power source to the computing device. In response to the network hardware triggering the physical line, the power supply interrupts providing the power to the computing device for a length of time to cause the computing device to restart and cold reboot.

Abstract: A method for recovering a basic input/output system (BIOS) image file of a computer system is provided. The method includes steps of: controlling a switch unit of the computer system to switch from a first state to a second state when the BIOS image file is to be updated; reading a current BIOS image file so as to store the same as a backup; controlling the switch unit to switch back to the first state; determining whether a command is received within a first predetermined time period when the BIOS image file is successfully updated to a new version of the BIOS image file; and when negative, controlling the switch unit to switch to the second state and writing the backup of the current version of the BIOS image file.

Abstract: A management device includes a processor that stores, in a second memory, power source information indicating first states of power sources of respective first electronic apparatuses included in an electronic apparatus group. The processor instructs, upon receiving a first instruction, the first electronic apparatuses identified by first apparatus information held in a first memory to transition the respective first states. The processor receives a second instruction to add a new electronic apparatus to the electronic apparatus group. The processor suppresses, in a case where any one of the first states is being transitioned, second apparatus information of the new electronic apparatus from being stored in the first memory. The processor stores the second apparatus information in the first memory in a case where transition of all the first states has been completed, and matches a second state of a power source of the new electronic apparatus with the first states.

Abstract: Sub-components assembled into a computer are selected based on sub-component power efficiency levels (for example, low, medium, high) and/or anticipated usage of the computer. Multiple units of each type of sub-component (for example, a CPU) are tested to determine a power efficiency level of each unit. Computers in which sub-component efficiency levels are desired to match an overall computer efficiency level, receive sub-component units of corresponding efficiency level. Computers anticipated to run applications that make intensive use of a given type of sub-component receive the given units having a higher efficiency level. Computers anticipated to run applications that make little use of a given type of sub-component receive a physical unit having a lower efficiency level. Computers anticipated to run a wide variety of applications of no particular usage intensity for a given type of sub-component, receive a unit having an average efficiency level.

Abstract: A signal processing circuit includes: a clock input terminal configured to receive a master clock from outside: a signal processing part configured to perform a signal processing based on the master clock; an interface circuit configured to communicate with an external circuit; and a clock detection circuit configured to determine, using a serial clock received by the interface circuit, whether the master clock is input.

Abstract: A system and method configured with an electronic device to enable prediction-based power management by providing direct transition to a lower power state such that overall energy consumption is reduced. The system and method includes an idleness information recording module configured to, using a power management agent, non-intrusively observe and record usage and idleness information of the electronic device, a learning module configured to, using a neural network operatively coupled with the power management agent, conduct deep learning of idleness patterns of the electronic device, a prediction module configured to predict future idleness of the electronic device based on the deep learning of the idleness patterns, and a prediction-based lower power state transfer module configured to directly transition the electronic device to lower power state based on the predicted future idleness.

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

Abstract: A power adapter device may use a method for efficient charging of multiple portable information handling systems based on learned charging characteristics. In particular, when electrical power is delivered to at least one of the portable information handling systems, the power adapter device may prioritize electrical power delivery to another portable information handling system ahead of the portable information handling systems based on the learned charging characteristics such that charging is efficient.