Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: Methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

Abstract: A processor-implemented method includes: determining a first multiplication matrix and a second multiplication matrix, based on an input multiplicand matrix and an input multiplier matrix that are generated from an input signal; determining a matrix to be restored, based on the first multiplication matrix and the second multiplication matrix; determining a matrix restoration constraint value, based on the matrix to be restored; determining a multiplication result of the input multiplicand matrix and the input multiplier matrix, based on the matrix restoration constraint value and the matrix to be restored; and analyzing the input signal based on the multiplication result.

Abstract: A circuit arrangement includes an array of MAC circuits, wherein each MAC circuit includes a cache configured for storage of a plurality of kernels. The MAC circuits are configured to receive a first set of data elements of an IFM at a first rate. The MAC circuits are configured to perform first MAC operations on the first set of the data elements and a first one of the kernels associated with a first OFM depth index during a first MAC cycle, wherein a rate of MAC cycles is faster than the first rate. The MAC circuits are configured to perform second MAC operations on the first set of the data elements and a second one of the kernels associated with a second OFM depth index during a second MAC cycle that consecutively follows the first MAC cycle.

Abstract: A processing-in-memory (PIM) device includes a data storage region and a multiplication/accumulation (MAC) operator. The data storage region is configured to store first data and second data. The MAC operator is configured to perform a MAC arithmetic operation of the first data and the second data. The MAC operator includes a MAC circuit configured to perform the MAC arithmetic operation to output MAC result data and a data output unit configured to feedback bias data to the MAC circuit prior to the MAC arithmetic operation.

Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.

Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a multiplier for performing a multiplying calculation of the first data and the second data. The arithmetic circuit is configured to perform a multiplication/accumulation (MAC) arithmetic operation of the first data and the second data. The arithmetic circuit includes a zero-detection circuit configured to disable input of the multiplier and to output zero data including multiple bits having a value of ‘0’ as output data of the multiplier, when all bits included in at least one of the first data and the second data have a value of ‘0’.

Abstract: An arithmetic device includes storage, a controller, and operation circuitry. The storage stores therein P-dimensional input vectors, P×N-dimensional matrixes, N-dimensional intermediate value vectors, and N-dimensional output vectors, and is capable of executing, in parallel, two or more of reading processing of the input vector, reading processing of the matrix, reading processing of the intermediate value vector, and writing processing of the output vector. The controller sets read timings of a first input vector, a first matrix, and a first intermediate value vector, and write timing of a first output vector, in operation processing including a D-dimensional processing loop. The operation circuitry calculates product of the first input vector and the first matrix, calculates sum of the product and the first intermediate value vector, and stores the sum as the first output vector in the storage.

Abstract: The technology disclosed relates to allocating available physical compute units (PCUs) and/or physical memory units (PMUs) of a reconfigurable data processor to operation units of an operation unit graph for execution thereof. In particular, it relates to selecting, for evaluation, an intermediate stage compute processing time between lower and upper search bounds of a generic stage compute processing time, determining a pipeline number of the PCUs and/or the PMUs required to process the operation unit graph, and iteratively, initializing new lower and upper search bounds of the generic stage compute processing time and selecting, for evaluation in a next iteration, a new intermediate stage compute processing time taking into account whether the pipeline number of the PCUs and/or the PMUs produced for a prior intermediate stage compute processing time in a previous iteration is lower or higher than the available PCUs and/or PMUs.

Abstract: A system to support a machine learning (ML) operation comprises a core configured to receive and interpret commands into a set of instructions for the ML operation and a memory unit configured to maintain data for the ML operation. The system further comprises an inference engine having a plurality of processing tiles, each comprising an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform tasks of the ML operation on the data in the OCM. The system also comprises an instruction streaming engine configured to distribute the instructions to the processing tiles to control their operations and to synchronize data communication between the core and the inference engine so that data transmitted between them correctly reaches the corresponding processing tiles while ensuring coherence of data shared and distributed among the core and the OCMs.

Abstract: A system for convolving an image includes a processing circuitry that retrieves the image including a set of rows, and a set of kernels, and merges serially all columns of each kernel, to generate a merged kernel. The processing circuitry executes parallelly multiple times, a multiply-accumulate (MAC) instruction on a row loaded in a corresponding vector register and a corresponding coefficient of the merged kernel and a load instruction on a subsequent row in one clock cycle. In the same clock cycle based on the MAC instruction, a logical shift operation is executed on the merged kernel to shift a current coefficient of the merged kernel with a subsequent coefficient such that the MAC instruction is executed on the subsequent row and the subsequent coefficient in the next clock cycle. Thus, each clock cycle is utilized by the system for executing both the MAC and load instructions.

Abstract: Systems, apparatuses and methods may provide for technology that recognizes, via a neural network, a pattern of memory access and compute instructions based on an input set of machine instructions, determines, via a neural network, a sequence of instructions to be offloaded for execution by the secondary computing device based on the recognized pattern of memory access and compute instructions, and translates the sequence of instructions to be offloaded from instructions executable by a central processing unit (CPU) into instructions executable by the secondary computing device.

Abstract: An example system implementing a processing-in-memory pipeline includes: a memory array to store a plurality of look-up tables (LUTs) and data; a control block coupled to the memory array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs; and a logic array coupled to the memory array and the control block, the logic array to perform, based on control inputs received from the control block, logic operations on the activated LUTs and the data.

Abstract: An apparatus performs vector matrix multiplication (VMM) for an analog neural network (ANN). The apparatus includes a column of NAND flash cells in series, where each NAND flash cell includes a control gate; a bit line connected to the column of NAND flash cells, where a current drawn from the NAND flash cells flows to the bit line; an integrator connected to the bit line; and a controller having programmed instructions to control the column of NAND flash cells by setting the voltage of the control gate of each NAND flash cell.

Abstract: The present invention relates to a method secured against side channel attacks performing an arithmetic operation of a cryptographic algorithm mixing Boolean and arithmetic operations, wherein said method is performed by a cryptographic device comprising a processing system having at least one hardware processor, and said operation has a first value (x) and a second value (y) as operands, comprising: —obtaining (S1) a first masked value (x?), a second masked value (y?), a first Boolean mask (rx), a second Boolean mask (ry), said first masked value (x?) resulting from masking said first value (x) by said first Boolean mask (rx) by performing a Boolean exclusive OR (XOR) operation between said first value (x) and said first Boolean mask (rx), and said second masked value (y?) resulting from masking said second value (y) by said second Boolean mask (ry) by performing a Boolean exclusive OR (XOR) operation between said second value (y) and said second Boolean mask (ry), —performing (S2) in any order a plurality o

Abstract: An apparatus can be configured to control a quantum memory of a quantum computer. The quantum memory can have a first qubit. The apparatus can comprise: a first-classical-register; a first-clock; a first-machine-language-buffer, that stores a first-machine-language-circuit; and a first-implementer. The first-machine-language-circuit includes: a first-timestamp; a first-qubit-identifier unique to the first qubit; a first-qubit-control-instruction; and a first-protected-location of the first-classical-register. The first-implementer can be configured to: read the first-machine-language-circuit from the first-machine-language-buffer; and read a first-control-value from the first-protected-location of the first-classical-register, the first-control-value can be configured to encode either a first-execute-instruction or a first-alternate-control-instruction.

Abstract: A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.

Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: A high-level synthesis multiprocessor system enables sophisticated algorithms to be easily realized by almost a smallest circuit. A shared memory is divided into a plurality of banks. The memory banks are connected to processors, respectively. Each processor receives an instruction code and an operand from its connected memory bank. After the operation execution, the processor sends the result to its adjacent processor element to set it as an accumulator value at the time of execution of a next instruction. A software program to be executed is fixed. A processor to execute each instruction in the software program is uniquely identified. Each processor has a function for executing its instruction out of all executable instructions in the multiprocessor system, and does not have a function for executing an instruction that the processor is not to execute. The circuit configuration with unused instructions deleted is provided.