Abstract: Techniques are disclosed relating to preventing a process from using state information to control a flow of execution of different process. Accordingly, a processor of a computing device may execute a first process and store state information usable to facilitate speculative execution of that first process. An operating system of the computing device may determine whether the first process is trusted by the operating system. The operating system may further schedule a second process for execution of the processor after executing the first process. In response to determining that the first process is not trusted, the operating system may cause the processor to execute one or more instructions before executing the second process. These one or more instructions may prevent the stored state information of the first process from affecting execution of the second process.

Abstract: Embodiments are directed to a processor having a functional slice architecture. The processor is divided into tiles (or functional units) organized into a plurality of functional slices. The functional slices are configured to perform specific operations within the processor, which includes memory slices for storing operand data and arithmetic logic slices for performing operations on received operand data (e.g., vector processing, matrix manipulation). The processor includes a plurality of functional slices of a module type, each functional slice having a plurality of tiles. The processor further includes a plurality of data transport lanes for transporting data in a direction indicated in a corresponding instruction. The processor also includes a plurality of instruction queues, each instruction queue associated with a corresponding functional slice of the plurality of functional slices, wherein the instructions in the instruction queues comprise a functional slice specific operation code.

Abstract: In an embodiment, a compiler for generating command bundles is configured to receive an execution definition that includes operations for execution. The compiler determines an ordered set of hardware functions corresponding to a hardware architecture to execute at least one operation. The hardware architecture may be selected from typical processor types or a command-aware hardware processor. The compiler generates a command bundle that includes a set of logically independent commands based on hardware functions and functionality of the hardware architecture to optimize execution of the operations. A command-aware hardware processor includes a hardware routing mesh that includes sets of routing nodes that form one or more hardware pipelines. Many hardware pipelines may be included in the hardware routing mesh. A command bundle is transmitted through a selected hardware pipeline via a control path, and is modified by the routing nodes based on execution of commands to achieve a desired outcome.

Abstract: A method comprises: compiling the code segment with a compiler; and determining, based on an intermediate result of the compiling, a resource associated with a dedicated processing unit and for executing the code segment. As such, the resource required for executing a code segment may be determined quickly without actually executing the code segment and allocating or releasing the resource, which helps subsequent resource allocation and further brings about a better user experience.

Abstract: A flexible Digital Signal Processor module includes a Filter unit comprising a multiplier and an adder, where the multiplier receives input from a memory and a Shift Register Lookup table. The Digital Signal Processor module may implement digital filters such as FIR or IIR filters by providing suitable filter coefficients from the memory and data values from the Shift Register Lookup table. An optional state machine may ensure synchronisation of addressing of the memory Shift Register Lookup table, and between multiple instances of the Digital Signal Processor module where these are required for a particular filter implementation. The proposed architecture offers additional modes of operation wherein operations other than filter implementations are supported.

Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive a software program represented as a set of interconnected Data-Flow Graphs (DFGs), each DFG specifying code instructions that perform a respective portion of the software program, to schedule execution of the DFGs in time alternation, and, for each DFG being scheduled, to configure at least some of the compute nodes and interconnects in the compute fabric to execute the code instructions specified in the DFG, and send to the compute fabric multiple threads that each executes the code instructions specified in the DFG.

Abstract: Provided are integrated circuits and methods for transposing a tensor using processing element array operations. In some cases, it may be necessary to transpose elements of a tensor to perform a matrix operation. The tensor may be decomposed into blocks of data elements having dimensions consistent with the dimensions of a systolic array. An identity multiplication may be performed on each block of data elements loaded into a systolic array and the multiplication products summed in column partitions of a results buffer. The data elements in the column partitions of results buffer can then be mapped to row partitions of a buffer memory for further processing.

Abstract: An apparatus has floating-point multiplying circuitry to perform a floating-point multiply operation to multiply first and second floating-point operands to generate a product floating-point value. Shared hardware circuitry of the floating-point multiplying circuitry is reused to also support a floating-point scaling instruction specifying an input floating-point operand and an integer operand, which causes a floating-point scaling operation to be performed to generate an output floating-point value corresponding to a product of the input floating-point operand and a scaling factor 2X, where X is an integer represented by the integer operand.

Abstract: A method for processing virtualization of computers that are part of a group into virtual computers is provided. The method includes obtaining relationship data from the computers, where the relationship data identifies parameters used to communicate within the group. Then, the method analyzes utilization parameters for each of the computers of the group. A visual model for proposed virtualization of the group of computers is then generated. The visual model identifies hosting machines designated to define a virtual computer for each of the computers, where the visual model provides a graphical illustration of the group of computers once converted to virtual computers. The method enables adjustment of the proposed virtualization of the group of computers. Then, an execution sequence of virtualization operations to be carried out is generated, if execution of the proposed virtualization is triggered, and the execution sequence is saved to storage and accessed upon execution.

Abstract: A system is controlled by solving a mixed-integer optimal control optimization problem using branch-and-bound (B&B) optimization that searches for a global optimal solution within a search space. The B&B optimization iteratively partitions the search space into a nested tree of regions, and prunes at least one region from the nested tree of regions before finding a local optimal solution for each region when a dual objective value of a projection of a sub-optimal dual solution estimate for each region into a dual feasible space is greater than an upper bound or lesser than a lower bound of the global optimal solution maintained by the B&B optimization.

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

Abstract: A method of instruction dispatch routing comprises receiving an instruction for dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order, different from the first rotation order, is associated with non-priority instructions; selecting an issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

Abstract: An event-processing unit for processing tokens associated with a state or state transition, herein also referred to as an event, of an external device is disclosed. The EPU allows token-processing schemes, in which the processing of incoming tokens and the further handling of a processing result by the EPU are determined not only by the token identifier, but also by the payload data of the incoming token or by data in the data memory. A flag-processing capability of a processing-control stage allows applying flag-processing operations such as logical operations to data obtained as a processing result of an ALU-processing operation. The result of these operations determines a subsequent handling of ALU-result data by the EPU. Thus, whether or not the ALU-result data is written to the data memory also influences the processing of any subsequent incoming tokens for which that data is used in the ALU-processing operation.

Abstract: An arithmetic processing device includes: a decoder configured to write an immediate value to a register in a case where an instruction to be executed is an instruction not involving data reading from the register; and a processor configured to read data from the register and write a computing result based on the read data to the register in a case where an instruction to be executed by the decoder is an instruction involving data reading from the register.

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus, and perform arithmetic operations on the input. Each processing element can generate an output partial sum based on the arithmetic operations, provide the input to a next processing element of the given row-oriented bus, without the input being processed by a processing element of the row located between the two processing elements that uses a different row-oriented bus. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

Abstract: An apparatus (2) comprises an instruction decoder (6) and processing circuitry (4). The instruction decoder (6) supports branch instructions for triggering a non-sequential change of program flow to an instruction at a target address, including: a branch-with-link instruction for which a return address is set for a subsequent return of program flow; and at least one target-checking type of branch instruction, for which when the branch is taken an error handling response is triggered when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction. For at least a subset of the at least one target-checking type of branch instruction, a branch target variant of the branch-with-link instruction is a permitted type of branch target instruction.

Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element of a given columnar bus can receive an input partial sum from a prior element of the given columnar bus, and perform arithmetic operations on the input partial sum. Each processing element can generate an output partial sum based on the arithmetic operations, provide the output partial sum to a next processing element of the given columnar bus, without the output partial sum being processed by a processing element of the column located between the two processing elements that uses a different columnar bus. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory.