Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Method (and apparatus) for producing a 3D target structure in lithographic material. Focus region of a laser writing beam travels through a scanning manifold through the lithographic material. In the focus region of the laser writing beam, an exposure dose is irradiated into the lithographic material, and a structure region is locally defined. At least one exposure data set which represents a local exposure dose for the scan manifold as a function of location is determined. A structure which approximates the target structure is defined based on at least one exposure data set. This structure is analyzed and at least one analysis data set which represents the analyzed structure is determined. Deviation data set which represents deviations of the already defined structure from the target structure is determined. At least one correction exposure data set is determined. Correction structure based on the at least one correction exposure data set is defined.

Abstract: The method of parking and charging the individual vehicle providing for reception by the control center of parking stations territorial network of information from the individual vehicle user about stop waypoints for vehicle parking and charging along his planned route, establishment of communication between the user and control unit of this parking station, mating the electric connector of the vehicle battery with the connector of the parking station parking/charging terminal, charging the battery and storage of the vehicle, testing the charged condition of the battery and operability of the electric vehicle, time control of vehicle connection/disconnection to/from parking terminal, provides mutual settlements between the user and parking operator, and also engages the lock to fix the vehicle at the parking terminal and disengages the lock to ensure use of the vehicle.

Abstract: A system for programming an eFuse array in an integrated circuit (IC) includes an eFuse data file which has a first plurality of bits. The system includes a data compression module which has an input coupled to receive the eFuse data file. The data compression module reduces the size of the eFuse data file and provides a compressed data file. The compressed data file has fewer bits than the eFuse data file. The system includes an eFuse controller which has an input coupled to receive the compressed data file. The eFuse controller programs the eFuse array to permanently store the compressed data file in the eFuse array.

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

Abstract: Disclosed are a system and a method for optimizing integrated circuit layout based on neural network.

Abstract: A solar charging system for the vehicle includes a first photovoltaic (PV) module, a second PV module serially connected to the first PV module, and a differential power processing (DPP) transformer that converts power generated from the first PV module and the second PV module by using a magnetic body having a multi-winding structure.

Abstract: Disclosed is an improved approach to implement sharing of delay calculations for replicated portions of a design, where input slews may be different between those replicated design portions. This allows the system to experience runtime improvements for timing analysis of electronic designs.

Abstract: A quantum system controller configured to perform conditional transport with just-in-time waveform selection is provided. The quantum system controller comprises a processing device configured to generate a set of processed waveform files configured to cause a quantum processor of the quantum computer to perform a quantum circuit; cause the processed waveform files to be preloaded to one or more arbitrary waveform generators; and causing at least one signal to be provided to the one or more arbitrary waveform generators to execute at least one of the preloaded processed waveform files, wherein the signals provided to arbitrary waveform generators to execute at least one of the preloaded waveform files is in response to the quantum system controller evaluating a conditional operation. The signals provided to the arbitrary waveform generators allow for the just-in-time selection a waveform selection not on an expected path of the quantum circuit.

Abstract: The present invention provides a novel quantum gate as an oracle that exists with a quantum idea based on the concept of an N-dimensional unitary space including a complex space, by introducing Riemannian geometry being non-Euclidean geometry in an N-dimensional Euclidean space, and simultaneously expanding the frame of the space. The quantum gate according to the present invention is used for a quantum computer operation using an operator that has a simultaneous calculation characteristic of simultaneously performing a plurality of calculations, and includes PPT indicating a proposition, CON indicating converse, INV indicating inverse, ANT indicating anti, MU indicating nothing, MGN+ or MGN? indicating infinity, and KU indicating fluctuation.

Abstract: A battery management system comprising: at least one battery comprising two or more sets of cells, each set of cells comprising one or more cells; a multiplexing switch apparatus connected to each set of cells; and at least one controller configured to use the multiplexing switch apparatus to selectively discharge the sets of cells based on at least one criterion. A battery pack comprising: at least one battery comprising two or more sets of cells, each set of cells comprising one or more cells; and an integrated switching control system comprising at least one switch connected to each set of cells, wherein the integrated switching control system is configured to control the at least one switch to discharge the sets of cells sequentially or selectively based on at least one criterion. A battery management method or a battery pack control method.

Abstract: Disclosed herein is a computer implemented method of correcting a timing failure of a network of conductors and repowering structures in an integrated circuit design using a reinforcement learning agent. The reinforcement learning agent comprises a neural network. The method comprises: receiving a graph comprising nodes and edges that encodes said network of conductors and repowering structures; and receiving a modification recommendation from said reinforcement learning agent in response to inputting said graph into said reinforcement learning agent.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Boundary cells are used to abut two standard cell blocks. A standard cell block for an integrated circuit device includes a first standard cell, and a first boundary cell disposed adjacent to the first standard cell and along a boundary of the standard cell block. The first boundary cell includes a first region, a first dummy region, and a first layer extension region. The first region is abutted with the first standard cell and the first dummy region. The first dummy region is abutted with the first layer extension region. The first region and the first dummy region each include one or more non-functional layers. The first region, the first dummy region, and the first layer extension region are of a first semiconductor type.

Abstract: An automated debugging method includes obtaining waveforms of signals recorded during execution of one or a plurality of tests on a first properly functioning version of a design and on a second faulty version of the design, extracting behavior patterns of the signals in the waveforms of the first design and behavior patterns of the signals in the waveforms of the second design, identifying one or more deviations in signals of the extracted behavior patterns, identifying a corresponding simulation time or time window and presenting to a user via an output device code of the second design pertaining to a deviation of the one or more deviations in corresponding behavior patterns of the extracted behavior patterns and the time or time window during which that deviation occurred.

Abstract: In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that create a system-level address map and create a report. A system description of an electronic system (e.g., integrated circuit (IC)) is received that includes configuration parameters. A tree representation of the system is created based on the interconnect of the system. Each port of the system is assigned a tree node. To create a corresponding system-level address map, the tree representation is traversed from target(s) to initiator(s), calculating the address transformation at each node. A report of the system-level address map is created, and defects such as address duplication, missing addresses, etc. can be identified and reported to the user.

Abstract: Embodiments of the disclosure can include various electrical assemblies. In one embodiment, an electrical assembly can include a module including at least one module switching element and an energy storage device, the or each module switching element and the energy storage device in the module arranged to be combinable to selectively provide a voltage source; and a shorting device directly connected to first and second terminals of the energy storage device, the shorting device including a first shorting switching element configured to be switchable between: a first switching state to isolate the first and second terminals from each other; and a second switching state to electrically connect the first and second terminals to short the energy storage device.

Abstract: An apparatus for automatically determining an electronic circuit diagram of a vehicle includes n system code determination unit configured to, when component codes of electronic components mounted on a vehicle are input, determine system codes of electronic systems configurable based on the electronic components, a circuit diagram determination unit configured to select and determine, from a circuit diagram database, standard circuit diagrams matched with the system codes determined by the system code determination unit, and a display unit configured to display the standard circuit diagrams determined by the circuit diagram determination unit to be matched with electronic systems predetermined for respective system codes.

Abstract: A method of fabricating a semiconductor device includes designing a layout of the semiconductor device, performing a routing step using a routing tool, performing an optical proximity correction (OPC) on the designed layout, and performing a photolithography process on a substrate using a photomask manufactured by the layout corrected by the OPC. Performing the routing step includes generating and storing an X×Y via structure in the routing tool, each of X and Y being an integer between 1 and 20, providing a low-level line and a high-level line, providing the X×Y via structure on a region where the low-level line and the high-level line overlap, and providing at least one routing line that passes through the X×Y via structure.

Abstract: Various embodiments provide for pin access location generation for one or more cells of a circuit design, which may be part of electronic design automation (EDA). Some embodiments facilitate pin access location generation by generating and using multiple graphs, which enable such embodiments to ensure that neighbor pins are not missed and to check for design rule violations.