Abstract: Provided is a lithography model simulation method. The method comprises receiving a first mask image, generating a second mask image by simulating an optical model on the first mask image, generating at least one third mask image by simulating a quenching model on the second mask image, and generating a resist image by performing machine learning on the first mask image, the second mask image, and the third mask image. The generating of the resist image comprises outputting first output data by convolving the first mask image with a first kernel, outputting second output data by convolving the second mask image with a second kernel, outputting third output data by convolving the third mask image with a third kernel, and adding together the first to third output data. Each of the first to third kernels is or includes a free-form kernel.

Abstract: Disclosed is a flip-flop unit design method comprising: analyzing signal delay of a clock control signal in a digital circuit; selecting a clock gating circuit among a plurality of types of clock gating circuits according to the signal delay, and coupling at least one edge-triggered flip-flop and the selected clock gating circuit to be a flip-flop unit, wherein the plurality of types of clock gating circuits enable or disable a first clock signal according to the clock control signal to generate a second clock signal, and the edge-triggered flip-flop transmits data at an edge of the second clock signal. The design method eliminates the glitch in the clock signal generated by the clock gating circuit, reduces the number of logic devices of the clock gating circuit, reduces the power consumption of the clock gating circuit. The design method is applicable to a flip-flop group with any number of edge-triggered flip-flops.

Abstract: Systems and methods of verifying a hardware processing circuit design for a digital system are disclosed. Three different computer models of the same hardware are implemented. The first computer model is implemented on a first sequence of action inputs and a second sequence of action inputs. The second computer model is implemented on the first sequence of action inputs and is allowed to idle until the first sequence is done. The architectural states of the second computer model are then recorded. The third computer model is implemented on the second sequence after having set the third computer model to the recorded architectural states. The outputs of the first computer model and the third computer model are implemented to check for functional consistency. The techniques described herein can be used to check digital designs for functional consistency, are sound and complete, and do not require an understanding of implementation details.

Abstract: Failure mode, effects, and diagnostic analysis (FMEDA) is performed on hardware Intellectual Property (IP) of an electronic system. The analysis includes accessing a library of safety library components, each safety library component containing failure mode characterizations and safety data about a hardware model; and compiling the safety library components and the hardware IP. The compiling includes mapping instances of hardware models in the hardware IP to corresponding safety library components and aggregating the characterizations and safety data of the corresponding components.

Abstract: An integrated circuit including: a first cell including first-a and second-a output pins, a first routing wire connecting the first-a output pin to the second-a output pin, a first-a via connecting the first-a output pin to the first routing wire, and a second-a via connecting the second-a output pin to the first routing wire; and a second cell including first-b and second-b output pins, a second routing wire connecting the first-b output pin to the second-b output pin, a first-b via connecting the first-b output pin to the second routing wire, and a second-b via connecting the second-b output pin to the second routing wire, wherein the first-a via is at a first-a position, the second-a via is at a second-a position, the first-b via is at a first-b position, the second-b via is at a second-b position different from each other.

Abstract: A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.

Abstract: A method is provided, including following operations: receiving, by a static voltage drop (SIR) prediction circuitry, floorplan data of a floorplan layout of a semiconductor device; generating a first SIR result by a machine learning model based on the floorplan data; generating a first similarity value based on a comparison of the floorplan data with a plurality of training data; generating a second SIR result based on the first SIR result and a first compensation value, corresponding to the first similarity value, in a mapping table; and generating a bump assignment data to update the floorplan data based on a comparison between the second SIR result with a plurality of predetermined SIR values.

Abstract: The present invention relates to a method for manufacturing a circuit board assembly, which includes: mounting a plurality of components on a circuit board; preparing a mold comprising a concave portion corresponding to a shape of each of the plurality of components and a convex portion corresponding to a surface of the circuit board; providing the mold at an upper side of the circuit board and preparing a protective material to be disposed on the circuit board; disposing the protective material on the circuit board and the components by using the mold; and curing the protective material to form a protective layer.

Abstract: An adaptable framework for circuit design simulation verification generates a simulation database for a circuit design and processed design data for the circuit design. The processed design data includes source files for the circuit design referenced by the simulation database. The simulation database and the processed design data are exported from a host integrated development environment (IDE). A template writer configured to generate a simulation script for the circuit design using the simulation database is provided. The simulation script is generated by executing the template writer. The simulation script is generated according to one or more user-specified parameters of the template writer using the simulation database and the processed design data as exported.

Abstract: Systems and methods transform frame-based algorithms into revised algorithms having the same behavior as the frame-based algorithms, but that can be synthesized in hardware. The frame-based algorithm may be represented by an executable simulation model, such as a block diagram model.

Abstract: A method of some embodiments receives an initial first physical design of a circuit. The method uses a machine-trained network to generate a second physical design that is a prediction of how the first physical design will look at a subsequent manufacturing stage. The method then uses the second physical design to modify the first physical design. Examples of such modifications include modifying a set of one or more routes in the first physical design and/or modifying a set of placement locations of a set of one or more sub-circuits or circuit components defined in the first physical design.

Abstract: A work support device according to the invention detects circuit symbols and conducting wires from circuit drawing data that does not have information unique to a circuit part, and by matching the detection result with a result of tracing a conduction path by handwriting by a worker, the circuit part and the conducting wire through which the conduction path passes are specified.

Abstract: A method for bit line alignment during the design of an integrated circuit is provided. Aspects include receiving a chip design for the integrated circuit and receiving an intended orientation of the integrated circuit. Aspects also include identifying one or more elements of the chip design that include word lines that are oriented in a substantially gravitational direction and modifying the chip design to perform one or more of rotating the one or more elements such that the word lines are no longer oriented in a substantially gravitational direction and rotating the one or more elements such that the word lines are oriented in a direction substantially perpendicular to the gravitational direction. Aspects further include causing the fabrication of the integrated circuit based on the modified chip design.

Abstract: A photonic integrated circuit (PIC) may be simulated by executing multiple iterations. Each iteration estimates outputs of the components in the PIC from inputs to the components. At least one output is estimated by running a simulation of the component. For at least one component and one iteration, the input for the current iteration is compared against a cached input for the component. Based on the comparison, it is determined whether to retrieve a corresponding cached output for the component or to run the simulation of the component.

Abstract: The present disclosure describes an interferometer interfering a plurality of bosonic particles at one or more inputs so as to form one or more first outputs, one or more second outputs, and one or more third outputs. The one or more third outputs output one or more purified bosonic particles depending on the presence of absence of bosonic particles at the first outputs and second outputs.

Abstract: An integrated circuit includes a first circuit cell having a first width and a second circuit cell having a second width that is wider than the first width by at least one contacted poly pitch. An equivalent circuit of the first circuit cell is the same as an equivalent circuit of the second circuit cell.

Abstract: Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.

Abstract: A battery charging apparatus includes a first converter coupled between an input voltage bus and a battery, and a second converter coupled between the input voltage bus and the battery, wherein switches of the first converter and switches of the second converter are integrated in a same semiconductor chip, and wherein the first converter and the second converter are configured to be coupled to a controller, the controller being configured to generate gate drive signals for configuring the first converter and the second converter during a charging process of the battery such that a load current distribution between the first converter and the second converter is controlled based on an input current limit of the battery charging apparatus.

Abstract: A first set of timing paths may be selected in an integrated circuit (IC) design. A first set of timing slack values may be calculated for the first set of timing paths across a first set of corners. A dominant corner may be selected in the first set of corners based on the first set of timing slack values. A second set of timing slack values for the dominant corner may be determined for a second set of timing paths in the IC design. A third set of timing slack values may be estimated for the second set of timing paths for non-dominant corners. The third set of timing slack values may be used to select a second set of corners for a timing path in the second set of timing paths, and circuit objects in the timing path may be marked with the second set of corners.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.