Abstract: Systems and methods transform frame-based algorithms into revised algorithms having the same behavior as the frame-based algorithms, but that can be synthesized in hardware. The frame-based algorithm may be represented by an executable simulation model, such as a block diagram model.

Abstract: A method of some embodiments receives an initial first physical design of a circuit. The method uses a machine-trained network to generate a second physical design that is a prediction of how the first physical design will look at a subsequent manufacturing stage. The method then uses the second physical design to modify the first physical design. Examples of such modifications include modifying a set of one or more routes in the first physical design and/or modifying a set of placement locations of a set of one or more sub-circuits or circuit components defined in the first physical design.

Abstract: A work support device according to the invention detects circuit symbols and conducting wires from circuit drawing data that does not have information unique to a circuit part, and by matching the detection result with a result of tracing a conduction path by handwriting by a worker, the circuit part and the conducting wire through which the conduction path passes are specified.

Abstract: A method for bit line alignment during the design of an integrated circuit is provided. Aspects include receiving a chip design for the integrated circuit and receiving an intended orientation of the integrated circuit. Aspects also include identifying one or more elements of the chip design that include word lines that are oriented in a substantially gravitational direction and modifying the chip design to perform one or more of rotating the one or more elements such that the word lines are no longer oriented in a substantially gravitational direction and rotating the one or more elements such that the word lines are oriented in a direction substantially perpendicular to the gravitational direction. Aspects further include causing the fabrication of the integrated circuit based on the modified chip design.

Abstract: A photonic integrated circuit (PIC) may be simulated by executing multiple iterations. Each iteration estimates outputs of the components in the PIC from inputs to the components. At least one output is estimated by running a simulation of the component. For at least one component and one iteration, the input for the current iteration is compared against a cached input for the component. Based on the comparison, it is determined whether to retrieve a corresponding cached output for the component or to run the simulation of the component.

Abstract: The present disclosure describes an interferometer interfering a plurality of bosonic particles at one or more inputs so as to form one or more first outputs, one or more second outputs, and one or more third outputs. The one or more third outputs output one or more purified bosonic particles depending on the presence of absence of bosonic particles at the first outputs and second outputs.

Abstract: An integrated circuit includes a first circuit cell having a first width and a second circuit cell having a second width that is wider than the first width by at least one contacted poly pitch. An equivalent circuit of the first circuit cell is the same as an equivalent circuit of the second circuit cell.

Abstract: Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.

Abstract: A battery charging apparatus includes a first converter coupled between an input voltage bus and a battery, and a second converter coupled between the input voltage bus and the battery, wherein switches of the first converter and switches of the second converter are integrated in a same semiconductor chip, and wherein the first converter and the second converter are configured to be coupled to a controller, the controller being configured to generate gate drive signals for configuring the first converter and the second converter during a charging process of the battery such that a load current distribution between the first converter and the second converter is controlled based on an input current limit of the battery charging apparatus.

Abstract: A first set of timing paths may be selected in an integrated circuit (IC) design. A first set of timing slack values may be calculated for the first set of timing paths across a first set of corners. A dominant corner may be selected in the first set of corners based on the first set of timing slack values. A second set of timing slack values for the dominant corner may be determined for a second set of timing paths in the IC design. A third set of timing slack values may be estimated for the second set of timing paths for non-dominant corners. The third set of timing slack values may be used to select a second set of corners for a timing path in the second set of timing paths, and circuit objects in the timing path may be marked with the second set of corners.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Method (and apparatus) for producing a 3D target structure in lithographic material. Focus region of a laser writing beam travels through a scanning manifold through the lithographic material. In the focus region of the laser writing beam, an exposure dose is irradiated into the lithographic material, and a structure region is locally defined. At least one exposure data set which represents a local exposure dose for the scan manifold as a function of location is determined. A structure which approximates the target structure is defined based on at least one exposure data set. This structure is analyzed and at least one analysis data set which represents the analyzed structure is determined. Deviation data set which represents deviations of the already defined structure from the target structure is determined. At least one correction exposure data set is determined. Correction structure based on the at least one correction exposure data set is defined.

Abstract: The method of parking and charging the individual vehicle providing for reception by the control center of parking stations territorial network of information from the individual vehicle user about stop waypoints for vehicle parking and charging along his planned route, establishment of communication between the user and control unit of this parking station, mating the electric connector of the vehicle battery with the connector of the parking station parking/charging terminal, charging the battery and storage of the vehicle, testing the charged condition of the battery and operability of the electric vehicle, time control of vehicle connection/disconnection to/from parking terminal, provides mutual settlements between the user and parking operator, and also engages the lock to fix the vehicle at the parking terminal and disengages the lock to ensure use of the vehicle.

Abstract: A system for programming an eFuse array in an integrated circuit (IC) includes an eFuse data file which has a first plurality of bits. The system includes a data compression module which has an input coupled to receive the eFuse data file. The data compression module reduces the size of the eFuse data file and provides a compressed data file. The compressed data file has fewer bits than the eFuse data file. The system includes an eFuse controller which has an input coupled to receive the compressed data file. The eFuse controller programs the eFuse array to permanently store the compressed data file in the eFuse array.

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

Abstract: Disclosed are a system and a method for optimizing integrated circuit layout based on neural network.

Abstract: A solar charging system for the vehicle includes a first photovoltaic (PV) module, a second PV module serially connected to the first PV module, and a differential power processing (DPP) transformer that converts power generated from the first PV module and the second PV module by using a magnetic body having a multi-winding structure.

Abstract: Disclosed is an improved approach to implement sharing of delay calculations for replicated portions of a design, where input slews may be different between those replicated design portions. This allows the system to experience runtime improvements for timing analysis of electronic designs.

Abstract: A quantum system controller configured to perform conditional transport with just-in-time waveform selection is provided. The quantum system controller comprises a processing device configured to generate a set of processed waveform files configured to cause a quantum processor of the quantum computer to perform a quantum circuit; cause the processed waveform files to be preloaded to one or more arbitrary waveform generators; and causing at least one signal to be provided to the one or more arbitrary waveform generators to execute at least one of the preloaded processed waveform files, wherein the signals provided to arbitrary waveform generators to execute at least one of the preloaded waveform files is in response to the quantum system controller evaluating a conditional operation. The signals provided to the arbitrary waveform generators allow for the just-in-time selection a waveform selection not on an expected path of the quantum circuit.

Abstract: The present invention provides a novel quantum gate as an oracle that exists with a quantum idea based on the concept of an N-dimensional unitary space including a complex space, by introducing Riemannian geometry being non-Euclidean geometry in an N-dimensional Euclidean space, and simultaneously expanding the frame of the space. The quantum gate according to the present invention is used for a quantum computer operation using an operator that has a simultaneous calculation characteristic of simultaneously performing a plurality of calculations, and includes PPT indicating a proposition, CON indicating converse, INV indicating inverse, ANT indicating anti, MU indicating nothing, MGN+ or MGN? indicating infinity, and KU indicating fluctuation.