Patents Examined by Eric D Lee
  • Patent number: 10534882
    Abstract: A method for configuring the features of an integrated circuit. In the method, the integrated circuit receives a feature vector message from a first party. The feature vector message is included in a response to a feature set request from the first party to a second party. The integrated circuit configures at least one feature of the integrated circuit based on a feature vector in the feature vector message. The integrated circuit generates an attestation result based on the at least one configured feature of the integrated circuit and using a key securely stored in the integrated circuit and known to the second party and not known to the first party. The integrated circuit forwards the attestation result to the first party.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: January 14, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Ivan McLean, Stuart Moskovics, Bryan Campbell, Mark Dragicevich
  • Patent number: 10528689
    Abstract: A system and methods to verify a correctness of data formatted according to an IEEE P1687 (IJTAG) standard, in connection with migration of test patterns from an instrument level to a top level of an integrated circuit design. Data describing an integrated circuit at the instrument level and at the top level is read from Instrument Connectivity Language (ICL) files, Procedural Description Language (PDL) files, and hardware description language (HDL) files. The methods include at least one of verifying structural descriptions of the integrated circuit in the ICL files and verifying an ability to use chip level inputs to access instruments in the integrated circuit. The verification procedure is performed prior to a simulation in which a migrated test pattern is applied to the integrated circuit.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 7, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Rajesh Khurana, Vivek Chickermane, Dhruv Dua, Krishna Vijaya Chakravadhanula
  • Patent number: 10521543
    Abstract: Disclosed herein are embodiments of systems, methods, and products for dynamically determining and rendering a target resistance of a partially routed net between two circuit devices in an integrated circuit (IC) design and automatically resizing a wire segment being edited in real time based on the target resistance such that the fully routed net satisfies the maximum resistance constraint. Therefore, the embodiments disclosed herein simplify the circuit designer's job and improves design productivity. Unlike conventional systems, an EDA tool disclosed herein does not have to route the full net between two circuit devices to run design rule checking (DRC). Thus, the EDA tool does not require multiple iterations of fully routing a net and checking for DRC violations such that the maximum resistance constraint is not violated.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 31, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Laurent Saint-Marcel
  • Patent number: 10515176
    Abstract: The present disclosure relates to a computer-implemented method for visualizing one or more IP-XACT component data routes is provided. The method may include receiving, using at least one processor, an IP-XACT description of one or design elements including at least one target ingress interface, and at least one of an initiator egress interface, a memory map and an address space. The method may further include analyzing, using the at least one processor, the IP-XACT description of the one or design elements and displaying a graphical user interface, based upon, at least in part, the IP-XACT description of one or design elements, wherein the graphical user interface is configured to display the at least one target ingress interface, and any number of the initiator egress interface, the memory map and the address space.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 24, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Uri Joel Maoz, Ronen Shoham
  • Patent number: 10515766
    Abstract: A capacitor includes a first plate and a second plate parallel to the first plate. An RF source includes a first line and a second line through which RF is fed. The first line is electrically connected to the first plate. The second line is passed through the first and second plates and then looped around the first and second plates, and the pass and loop of the second line is repeated at least once. The second line is then passed through the first plate and electrically connected to the second plate to form a capacitor having negative capacitance.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 24, 2019
    Inventor: Choon Sae Lee
  • Patent number: 10516286
    Abstract: The invention relates to an inductive charging device for charging at least one battery, in particular at least one portable power tool battery, with a charging unit provided for transferring electrical energy to the at least one battery, and with a detector unit provided for detecting a removal of the at least one battery during a charging process. It is proposed that the detector unit includes at least one sensor provided for monitoring at least a resonance voltage and/or at least a resonance current of the charging unit.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 24, 2019
    Assignee: Robert Bosch GmbH
    Inventor: Juergen Mack
  • Patent number: 10503865
    Abstract: A photonic design automation (PDA) tool to facilitate design of semiconductor photonic devices is described. In one example, the PDA tool includes a process design library including one or more photonics parameterized cells (pCells), a plurality of processor-executable photonics design functions including a design rule check (DRC) violation removal function, and a semiconductor technology-dependent parameter file including a plurality of design rules that define allowed semiconductor design patterns to be converted to a plurality of semiconductor fabrication mask designs in a first semiconductor technology. The PDA tool supports a graphical user interface (GUI) to provide access to the library of photonic pCells to create intuitive physical property layers for a photonic device, and processes the physical property layers using the DRC violation removal function and the design rules to automatically generate a plurality of mask design layers for a “DRC clean” physical layout of the photonics device.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 10, 2019
    Assignee: Massachusetts Institute of Technology
    Inventor: Luca Alloatti
  • Patent number: 10491015
    Abstract: An electronic device and an operation method thereof are provided. The electronic device includes a connecting unit configured to connect to an external power supply device that provides power to the electronic device; a first power managing unit configured to drive the electronic device using power provided from a first external power supply device connected to the connecting unit; a second power managing unit configured to charge a battery contained in the electronic device using power provided from a second external power supply device connected to the connecting unit; and a switching module configured to connect the connecting unit to one of the first power managing unit and the second power managing unit. Also, connection pins are not configured redundantly and respectively for external power supply devices, but a connecting unit is unified through a single common wiring and is commonly used, and thus, a wiring and components for supplying power may be reduced.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Eun-Seok Hong
  • Patent number: 10467364
    Abstract: In some embodiments, a plurality of first input waveforms having a same first input transition characteristic and different first tail characteristics are obtained. A first cell is characterized using the plurality of first input waveforms to create a plurality of corresponding first entries associated with the first input transition characteristic in a library. A design layout is generated based on performing circuit simulation using at least one entry of the plurality of first entries. An integrated circuit (IC) chip is manufactured using the design layout.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang
  • Patent number: 10460068
    Abstract: A system for semiconductor chip fabrication. A host system hosts a capacitance adjust tool for performing calculating a ground capacitance adjust for a wire segment going through routing tiles according to the following operations; providing the routing tiles having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires; computing ground capacitance adjusts for a victim wire averaged across all aggressor slew values and across possible spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, to guide placement of the wire segment in the routing tiles to avoid coupling noise; and outputting the placement of the wire segments to a tool for manufacturing the semiconductor chip.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald D. Rose, Vladimir Zolotov
  • Patent number: 10460064
    Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gracieli Posser, Wen-Hao Liu, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10460063
    Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10460065
    Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li, Charles Jay Alpert
  • Patent number: 10460066
    Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gracieli Posser, Wen-Hao Liu, Wing-Kai Chow, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10432013
    Abstract: A solar charging system for a portable electronic device includes an electrical connector adapted to be removably coupled to an electrical interface of the portable electronic device. A rechargeable battery is electrically coupled to the electrical connector, and the rechargeable battery is adapted to store a stored electrical power. A solar panel is electrically coupled to the rechargeable battery such that the received electrical power is stored in the rechargeable battery as stored electrical power. When the electrical connector is electrically coupled to the electrical interface of the installed portable electronic device, stored electrical power is provided or conveyed to the portable electronic device. When the electrical connector is not electrically coupled to the electrical interface of the installed portable electronic device, the received electrical power is stored in the rechargeable battery as stored electrical power.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: October 1, 2019
    Assignee: OTTER PRODUCTS, LLC
    Inventors: Christopher R. Langlois, Dane A. Sprister, Zachariah J. Pickett
  • Patent number: 10423754
    Abstract: In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to a design technique that can determine an optimal number and placement of ESD cells in a design for an IC. In embodiments, the technique includes determining an effective resistance criteria between a set of candidate ESD cells to the bumps/pads of the IC and finding a minimum set of ESD cells that covers all the bumps/pads. In embodiments, the technique is employed at the early stage of the design of the IC.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: September 24, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Nityanand Rai, Xin Gu, Zhiyu Zeng
  • Patent number: 10421371
    Abstract: The invention relates to a system for charging an electric vehicle, comprising a measuring device which is designed to measure a charge voltage on a charging interface of the electric vehicle, an evaluation device which is designed to determine first characteristic variables from the measured charge voltage, a communication device which is designed to transfer the first characteristic variables to other electric vehicles and/or to capture, from the other electric vehicles, second characteristic variables relating to charge voltages of the other electric vehicles, a control device which is designed to control, in accordance with the first and/or second characteristic variables, the charge power withdrawn from an energy supply network by the electric vehicle by means of the charging interface. The invention also relates to an electric vehicle and a method.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: September 24, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Ian Faye, Bernd Eckert
  • Patent number: 10417370
    Abstract: Quantum computations based on second quantization are performed by applying one body and two body terms in a selected order. Typically, terms associated with operators that commute are applied prior to application of other terms. In a particular example, one body terms of the form hpp are applied first, followed by two body terms of the form hprrp.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: September 17, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Matthew Hastings, David Wecker
  • Patent number: 10409945
    Abstract: Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection candidate of a plurality of connection candidates for the partition to generate proof results for the partition. These techniques may further additionally generate a property for a connection candidate that fails to result in definitive proof results and prove or disprove the property with formal methods or techniques.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: September 10, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chung-Wah Norris Ip, Georgia Penido Safe, Guilherme Henrique de Sousa Santos, Adriana Cassia Rossi de Almeida Braz
  • Patent number: 10409947
    Abstract: According to one general aspect, a method may include receiving a data file that includes placement data regarding a plurality of circuit cells. The circuit cells may include respective layout portions. The layout portions may be associated with a plurality of respective lithographic colors. The method may include determining if a violating circuit cell is to be re-colored. The method may include indicating that, via at least one shape on a color swap layer in the data file, the violating circuit cell is to be at least partially re-colored. A color swap layer shape may cause a mask generator to re-color the portion of the violating circuit cell indicated by the color swap layer shape.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: David A. Petermann, Andrew P. Hoover, Chandrakanth Ramesh