Patents Examined by Eric D Lee
  • Patent number: 11227093
    Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitances, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Nan Yang, Wan-Yu Lo, Chung-Hsing Wang, Hiranmay Biswas
  • Patent number: 11222160
    Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: January 11, 2022
    Assignee: Synopsys, Inc.
    Inventor: Thomas Christopher Cecil
  • Patent number: 11216605
    Abstract: A computer implemented method is disclosed relating to the design of electronic circuits and systems. In some examples, a graphical user interface is utilized to receive first information relating to a requested electronic circuit. The first information includes a selected type of electronic circuit and one or more operating criteria relating to requested fundamental functionality of the selected type of electronic circuit. Second information is also received, relating to requested secondary attributes of a hypothetical candidate electronic circuit that satisfies the first information. In response, a set of candidate circuit architectures are displayed satisfying the first information, as well as a visualization of how each of the candidate circuit architectures relates to the second information.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: January 4, 2022
    Assignee: S3 Fuzion, Inc.
    Inventors: Edward Paul Osburn, Ian James Cain
  • Patent number: 11210448
    Abstract: Embodiments provide for mitigating parametric yield loss of an integrated circuit (IC) design. In certain embodiments, a delay distribution associated with at least one cell disposed in the design is determined. A pin slack distribution associated with paths in which the at least one cell is disposed is determined. A residual distribution is determined based at least in part on the delay distribution and the pin slack distribution. Yield loss associated with the at least one cell is determined based at least in part on the delay distribution and the residual distribution. When it is determined that that the yield loss associated with the at least one cell exceeds a yield loss threshold, the at least one cell may be identified as a candidate for replacement with a replacement cell.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 28, 2021
    Assignee: Synopsys, Inc.
    Inventors: Kelvin Le, Wenwen Chai, Li Ding
  • Patent number: 11165271
    Abstract: A control device for controlling charging of a non-aqueous metal air battery, the control device being configured to: determine a CO2 concentration (Cx) and an increase rate (RCO2) of CO2 concentration in the battery, charge the battery in case both the CO2 concentration (Cx) before starting charging exceeds a predetermined CO2 threshold (CT) and the increase rate of the CO2 concentration (RCO2) during charging is below a predetermined threshold value (?CT/?AhT, ?CT/?t), and stop charging when the increase rate (RCO2) exceeds the predetermined threshold value (?CT/?AhT, ?CT/?t). Also, a corresponding method of controlling charging of a rechargeable battery.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: November 2, 2021
    Assignee: TOYOTA MOTOR EUROPE
    Inventors: Fanny Barde, Keita Komiyama
  • Patent number: 11157661
    Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 26, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Vinayak Veer Vats, Sidharth Bhatia, Garrett Ho-Yee Sin, Pramod Nambiar, Hang Yu, Sanjay Kamath, Deenesh Padhi, Heng-Cheng Pai
  • Patent number: 11144688
    Abstract: A computer/software tool for electronic design automation (EDA) uses parasitic elements from a post-layout netlist (PLN) file for a given IC design to assess routing-imposed RC-based signal degeneration. The computer/software tool facilitates selection of, and insertion location for, one or more “virtual repeaters,” based on modification to the PLN file. The tool generates a visual display based on the calculated design characteristics, facilitating adjustment and optimization of repeater cell and location by the designer. The repeater insertion is “virtual,” because modeling and adjustment can be based on abstractions (e.g., load capacitance presented by a repeater) and the already-extracted netlist file, and because an actual circuit design need not be created until after a designer has fine-tuned repeater insertion parameters.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 12, 2021
    Assignee: Diakopto, Inc.
    Inventors: Maxim Ershov, Andrei Tcherniaev
  • Patent number: 11144700
    Abstract: Route segments of a set of nets may be grouped into route groups. Terminals of the set of nets may be grouped into terminal groups. For each net in the set of nets, a net signature may be determined based on route groups associated with the net and terminal groups associated with the net. The set of nets may be grouped into net groups based on the net signatures.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Kai-Ping Wang, Iris E. Chen
  • Patent number: 11132489
    Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 28, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Derong Liu, Yi-Xiao Ding, Zhuo Li, Mehmet Can Yildiz
  • Patent number: 11126766
    Abstract: A system and method is provided for element quality improvement in three-dimensional (3D) quadrilateral-dominant surface meshes. The system may include a processor configured to collapse a first plurality of edges of a plurality of quadrilateral elements that form a surface mesh of a 3D model, which edges have lengths that are shorter than a predetermined fraction of a minimum element edge length (MEL). Further, the processor may also move nodes connected to at least some of a second plurality of edges of the plurality of quadrilateral elements so as to have lengths that are at least the MEL. Also, the processor may adjust included angles and the warp of elements to be within predetermined limits. Further, the processor may collapse in the mesh all remaining edges of the plurality of quadrilateral elements that are shorter than the MEL to produce a modified surface mesh in which all quadrilaterals in the modified mesh have edge lengths that are at least the MEL.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 21, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Jonathan Makem, Nilanjan Mukherjee
  • Patent number: 11120193
    Abstract: A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Kurtz, Mark A. Lavin, Ronald D. Rose, Richard W. Taggart, Vladimir Zolotov
  • Patent number: 11120181
    Abstract: Systems and methods are provided to detect and determine the location and relative significance of joint damage in structures including bridges, and particularly including accelerated bridge construction (ABC) bridges, based on measured changes in bridge dynamic or static response parameters and model updating methods. These systems and methods may use a detailed finite element model to calculate the sensitivity of joint damages in the structure response parameters for a particular loading configuration and the change of state in the structure obtained through instrumentation and response monitoring of the structure compared to a prior condition of the structure in order to identify potential damages.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: September 14, 2021
    Assignee: THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEES
    Inventors: Mohammad Abedin, Armin Mehrabi
  • Patent number: 11106851
    Abstract: Disclosed approaches for processing a circuit design include interrupting processing of a circuit design by an electronic design automation (EDA) tool at a selected phase of processing. The tool serializes EDA state data into serialized state data while processing is interrupted and writes the serialized state data for subsequent restoration of tool state. To resume processing at the point of interruption, the EDA tool can read the serialized state data and deserialize the serialized state data. The EDA tool bypasses one or more phases of processing after reading the serialized state data and thereafter resumes processing of the circuit design.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 31, 2021
    Assignee: XILINX, INC.
    Inventors: Paul D. Kundarewich, Grigor S. Gasparyan, Mehrdad Eslami Dehkordi, Guenter Stenz, Xiao Dong
  • Patent number: 11101672
    Abstract: A secondary battery protection apparatus includes a plurality of secondary battery protection apparatuses. One of two adjacent secondary battery protection apparatuses includes a voltage determination unit that is not affected by a current transfer signal and configured to receive, through a single communication line, the current transfer signal that is transmitted from the other of the two adjacent battery protection apparatuses through the single communication line and an information element based on changes of a voltage value of a voltage transfer signal, and a current determination unit that is not affected by the voltage transfer signal and configured to receive, through the single communication line, the voltage transfer signal that is transmitted from the other of the two adjacent secondary battery protection apparatuses through the single communication line and an information element based on changes of the current value of the current transfer signal.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 24, 2021
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventor: Kohei Shibata
  • Patent number: 11100271
    Abstract: Seamless transitions between routing modes are provided via providing a cursor in association with a design layout; in response to receiving a follow-the-cursor (FTC) command at a first position in the design layout, create a first trace in the design layout where the cursor is displayed; in response to receiving a start command for point-to-point routing at a second position in the design layout: complete the first trace at the second position; and provide an indicator at the second position; in response to receiving an end command for point-to-point routing at a third position in the design layout: create a second trace in the design layout where the cursor is displayed; and create a third trace in the design layout, wherein the third trace is routed from the first trace to the second trace.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 24, 2021
    Assignee: Synopsys, Inc.
    Inventors: Mysore Sriram, Praveeen Yadav, Philippe Aubert McComber
  • Patent number: 11080445
    Abstract: A method for predicting an operation parameter of an integrated circuit includes the following steps. A plurality of cells used by the integrated circuit are provided. A voltage-frequency sweep test is performed on each of cells through a test model to generate a plurality of parameters, wherein the parameters correspond to a voltage value. A lookup table is established according to the parameters. A timing signoff corresponding to the integrated circuit is obtained. A timing analysis is performed on a plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain a critical timing path, and the operation parameter of the integrated circuit is predicted according to the critical timing path.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 3, 2021
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Yi Li, Xiaojing Li, Miao Liu
  • Patent number: 11079684
    Abstract: A measurement apparatus and method for determining a substrate grid describing a deformation of a substrate prior to exposure of the substrate in a lithographic apparatus configured to fabricate one or more features on the substrate. Position data for a plurality of first features and/or a plurality of second features on the substrate is obtained. Asymmetry data for at least a feature of the plurality of first features and/or the plurality of second features is obtained. The substrate grid based on the position data and the asymmetry data is determined. The substrate grid and asymmetry data are passed to the lithographic apparatus for controlling at least part of an exposure process to fabricate one or more features on the substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 3, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Franciscus Godefridus Casper Bijnen, Edo Maria Hulsebos, Henricus Johannes Lambertus Megens, Robert John Socha, Youping Zhang
  • Patent number: 11074388
    Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 27, 2021
    Assignee: Coventor, Inc.
    Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
  • Patent number: 11068638
    Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 11062070
    Abstract: Systems or methods of the present disclosure may facilitate meeting connectivity demands between the dies of the modularized integrated circuits. Such an integrated circuit system may include a first die of programmable fabric circuitry that is communicatively coupled to a second die of modular periphery intellectual property (IP) tile via a modular interface. The modular interface may enable communication between a first microbump of the first die and a second microbump of the second die using a time-division multiplexing (TDM) technique. The modular interface may also enable communication between the first microbump and the second microbump using a wire-to-wire connection that does not comprise the TDM technique.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Chee Hak Teh