Abstract: A method is disclosed for solving the Lagrangian dual of a constrained binary quadratic programming problem. The method comprises obtaining a constrained quadratic binary programming problem; until a convergence is detected, iteratively, performing a Lagrangian relaxation of the constrained quadratic binary programming problem to provide an unconstrained quadratic binary programming problem, providing the unconstrained quadratic binary programming problem to a quantum annealer, obtaining from the quantum annealer at least one corresponding solution, using the at least one corresponding solution to generate a new approximation for the Lagrangian dual bound; and providing a corresponding solution to the Lagrangian dual of the constrained binary quadratic programming problem after convergence.

Abstract: Systems and methods are described to accurately extract device parameters and optimize the design of macroscopic superconducting structures, for example qubits. This method presents the advantage of reusing existing plaquettes to simulate different processor topologies. The physical elements of a qubits are extracted via plurality of plaquettes. Each plaquette contains at least one physical element of the qubit design and has two ports on each side. Each plaquette is concatenated to at least one other plaquette via two ports. The values of inductance (L), capacitance (C) and mutual inductance (M) and quantum critical point of the qubit design can be computed. Changing the physical elements of the qubit design and iterating the method allows to effortlessly refine the qubit design.

Abstract: Provided are a wireless charging system, a wireless charging device and a wireless charging method. The wireless charging device includes a voltage conversion circuit, a wireless transmitter circuit and a communication control circuit. The voltage conversion circuit is configured to receive an input voltage and convert the input voltage to obtain an output voltage and an output current. The wireless transmitter circuit is configured to transmit an electromagnetic signal according to the output voltage and the output current of the voltage conversion circuit to perform wireless charging on a device to be charged. The communication control circuit is configured to perform wireless communication with the device to be charged during the wireless charging, to adjust a transmitting power of the wireless transmitter circuit, such that the transmitting power matches a charging voltage and/or a charging current required by a present charging stage of the battery.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: Systems and method for generating Ethernet modules based on base designs. After a processor receives a base design for an industrial device assembly, the processor may calculate electrical load limits for sections of the base design based on dimensions of the sections, a number of sections, a location of the industrial device assembly, and the like. Based on the electrical load limits, the processor may determine a number of Ethernet modules for the sections and respective placements of the Ethernet modules within the base design. The processor may update a layout of the industrial device assembly based on the number of Ethernet modules for the sections and respective placements of the Ethernet modules within the base design.

Abstract: A vehicle has a battery including a plurality of cells connected in series, and a battery management integrated circuit including a plurality of inputs each being directly electrically connected to a terminal of one of the cells via an electrical path that includes a fuse and a resistor connected in series. The battery management integrated circuit further includes a top input directly electrically connected to a positive output of the battery and configured to receive power from the battery that is defined by a current having a magnitude that is at least an order of magnitude greater than current received by the inputs and a voltage equal to a sum of voltages of all the cells.

Abstract: Implementations of a method of designing a module semiconductor product may include receiving a selection of a module type, one or more die, a placement of one or more wires, clips, or pins; and generating, using a processor, a module configuration file. The method may include generating a module bonding diagram using a build diagram system module; selecting one or more SPICE models corresponding with the die; and generating a product SPICE model and a three dimensional model for the module semiconductor product. The method may include generating one or more datasheet characteristics of the module semiconductor product with at least the product SPICE model and the product simulation module, generating a product datasheet for the module semiconductor product using the datasheet formation module, and providing access to at least the module bonding diagram, the product SPICE model, the three dimensional model, and the product datasheet to the user.

Abstract: The application relates to a charging system, including a number of m chargers each adapted for providing electrical energy to charge an electrical vehicle, whereby m is an integer and m?1, a number of n outlet ports each adapted for electrically connecting the electrical vehicle, whereby n is an integer and n?2, and a switchable connection matrix device including a number of n outlet port switches each adapted for electrically connecting at least one of the m chargers to one of the n outlet ports and, if m>1, a number of m?1 charger switches each adapted for electrically connecting two of the m chargers, whereby the switchable connection matrix device is adapted for detecting a short-circuit between at least two outlet ports and/or for generating a fault signal if the short-circuit between at least two outlet ports is detected.

Abstract: Various implementations described herein are directed to an apparatus having a processor and memory having instructions stored thereon that, when executed by the processor, cause the processor to identify conductive paths in a physical layout of an integrated circuit having nodal features that define a connective structure of the integrated circuit. The instructions may cause the processor to traverse the conductive paths to detect valid metals and redundant metals. The valid metals may refer to valid conductive paths between the nodal features that conjoin the nodal features. The redundant metals may refer to unused conductive paths that provide disjointed paths from the nodal features. The instructions may cause the processor to indicate the valid metals as marked with a first indicator and to indicate the redundant metals as unmarked with a second indicator that is different than the first indicator.

Abstract: Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, an image of an electronic circuit and storing an electronic circuit design file. Embodiments may further include identifying the electronic circuit design file based upon, at least in part, the image of the electronic circuit. Embodiments may also include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device.

Abstract: A contactless motor vehicle-charging device which, as components, includes a primary side and a secondary side, between which, via at least one air gap, energy can be transferred via inductive and/or capacitive coupling, and each of the components in each case includes at least a portion of a control circuit of the contactless motor vehicle-charging device, wherein at least one of the components includes a field controller and at least one of the components comprises a field measurement device which is designed to acquire a magnetic and/or electric field strength, wherein the field controller is designed to use in at least one control operation the acquired field strength as an actual value and, by this actual value and a predetermined setpoint value, to set at least one field strength of the contactless motor vehicle-charging device as a control variable.

Abstract: Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.

Abstract: A system for autonomous generative design in a system having a digital twin graph a requirements distillation tool for receiving requirements documents of a system in human-readable format and importing useful information contained in the requirements documents into the digital twin graph, and a synthesis and analysis tool in communication with the digital twin graph, wherein the synthesis and analysis tool generates a set of design alternatives based on the captured interactions of the user with the design tool and the imported useful information from the requirements documents. The system may include includes a design tool with an observer for capturing interactions of a user with the design tool, In addition to the observer, an insighter in communication with the design tool and with the digital twin graph receives design alternatives from the digital twin graph and present the receive design alternatives to a user via design tool.

Abstract: Disclosed is an improved approach to implement analog or mixed-signal designs. A method, system, and computer program product are provided to fully automate the analog placement step using a virtual grouping methodology which considers variable components and uses a genetic placement algorithm to find the best placement solution which fully respects the analog constraints defined by a user or auto identified by a tool.

Abstract: Implementing an asymmetric memory having random port ratios using memory primitives can include detecting, using computer hardware, a hardware description language (HDL) random access memory (RAM) within a circuit design. The HDL RAM is asymmetric. Using computer hardware, a number of a plurality of memory primitives needed to implement the HDL RAM as a RAM circuit are determined based on a maximum port width ratio of the memory primitives defined as 1:N and a port width ratio of the HDL RAM defined as 1:M, wherein each of M and N is an integer and a power of two and M exceeds N. The RAM circuit is asymmetric. Using the computer hardware, a write circuit and/or a read circuit can be generated for a first port of the RAM circuit. Further, using the computer hardware, a write circuit and/or a read circuit can be generated for a second port of the RAM circuit.

Abstract: A method of validating support circuits of a qubit array includes generating virtual control waveforms from one or more abstracted support circuits of the qubit array. An abstracted pulse sequence is created from the virtual control waveforms. The abstracted pulse sequence is converted into waveforms. The waveforms are sent to individual qubits of the qubit array. Output data from the qubit array is captured in response to the sent waveforms.

Abstract: There is presented a method for wirelessly charging, a plurality of rechargeable devices, wherein at least one rechargeable device is an ear level device, such as a hearing aid, said method including appointing a master device among the plurality of rechargeable devices, for each of the remaining rechargeable devices, transmitting information regarding a current battery status to the master device, such as wherein the step of transmitting information regarding battery status to the master device is carried out via a first communication channel, determining a charging profile of one or more rechargeable devices based on the plurality of information regarding current battery status, charging the one or more rechargeable devices based on, such as according to, the charging profile, such as wherein communication between the master device and a charger is carried out via a second communication channel such as a wireless communication channel, such as Bluetooth® or Bluetooth Low Energy or proprietary protocol).