Abstract: Systems, computer-implemented methods, and computer program products that can facilitate quantum topological classification are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a topological component that employs one or more quantum computing operations to identify one or more persistent homology features of a topological simplicial structure. The computer executable components can further comprise a topological classifier component that employs one or more machine learning models to classify the topological simplicial structure based on the one or more persistent homology features.

Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: generating a first embedding for a semiconductor element to be placed in a canvas based on feature information and logical design information of the semiconductor element by using a first neural network; and generating a probability distribution for placing the semiconductor element based on the first embedding and a second embedding for semiconductor elements already placed in the canvas by using a second neural network.

Abstract: A method of driving design on gate electrodes includes steps of: determining position information of a gate-on-array (GOA) device in an available drawing space according to a size design information and a resolution design information of a display panel, based on user configuration; determining target GOA design strategy information used for a current gate electrode driving design among a plurality of preset GOA design strategies; and drawing a GOA device pattern in the available drawing space of the GOA device, based on the target GOA design strategy information.

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Abstract: An integrated circuit structure includes a first and second power rail extending in a first direction and being located at a first level, a first and second set of conductive structures located at a second level and extending in a second direction, a first and second set of vias, and a first and second conductive structure located at a third level and extending in the second direction. The first set of vias coupling the first power rail to the first set of conductive structures. The second set of vias coupling the second power rail to the second set of conductive structures. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and the second set of conductive structures.

Abstract: Methods and apparatus for pattern matching and classification are disclosed. In one example of the disclosed technology, a method of performing pattern matching according to a puzzle-matching the methodology includes analyzing an original source layout pattern and determining a signature for the original source layout pattern. A target layout is scanned to search for one or more portions of the target layout that have a signature that matches or is similar to the signature of the original source pattern. Similar patterns are searched based on a signature comparison of the source pattern and the target layout. In some examples of the disclosed technology, it is possible to match partial context to the original source pattern. In some examples, matches can be made in the target layout for different orientations of layout.

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: A tool is disclosed that includes a discriminant module. The discriminant module finds one configuration, which is selected from many different possible and legal configurations, that is optimal. The optimal configuration is translated into a set of optimized parameters (identified from the library of parameters that the user can select from) and provided to the designer. The designer reviews (and can manually revise or change) the optimized parameters. The optimized parameters are translated into engineering parameters. The engineering parameters are passed, as an input, to the RTL generation module. The RTL generation module produces the RTL description of the hardware function that is optimal and meets the designer's defined requirements.

Abstract: A method for the development of a compilation process for a quantum circuit on a quantum processor, includes an implementation step of the compilation method including an iteration loop successively including: a step of simulation of a given implementation of the logical qubits on the physical qubits of the quantum processor; a step of detecting, in the quantum circuit, ineffective quantum gate(s); a step of estimating the number of quantum swap gates to be inserted into the quantum circuit so that all of the quantum gates of the quantum circuit are effective; and a retroaction step, by way of a simulated annealing, involving a new step of simulation, until attaining, whereupon all the quantum gates are effective: either a minimum threshold of the number of estimated quantum value swap gates between two physical qubits, or a maximum threshold of iterations in the loop.

Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

Abstract: A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

Abstract: An anti-warping design method for designing a resin molded article on a programmed computer includes dividing the molded article into a plurality of small elements, calculating sensitivity values for at least part of the elements with respect to warpage of the molded article, and displaying a distribution of the sensitivity values.

Abstract: Training of a machine learning model used to infer estimated delays of circuit routes during placement and routing of a circuit design. Training can include selecting sample pairs of source pins and destination pins of an integrated circuit (IC) device, and determining respective delays of shortest paths that connect the source pins to the destination pins of the sample pairs based on a resistance-capacitance model of wires that form the shortest paths on the IC device. Respective sets of features are determined for the shortest paths, and the model is trained using the respective sets of features and the respective delays as labels. The machine learning model can be provided to an electronic design automation tool for estimating delays.

Abstract: A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a defect rate in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.

Abstract: A method and a system for recording an integrated circuit version are provided. The method is adapted to a register in an integrated circuit, which includes the following steps: recording the integrated circuit version with N bits, in which N is an integer greater than 1; and amending only a bit value of at least one bit selected from the N bits that have not been used for denoting any past integrated circuit version each time when the integrated circuit is revised.

Abstract: Systems and methods are disclosed for to generation of dynamic design flows for integrated circuits. For example, a method may include accessing a design flow configuration data structure, wherein the design flow configuration data structure is encoded in a tool control language; based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein each flowmodule provides an application programming interface, in the tool control language, to a respective electronic design automation tool; based on the design flow configuration data structure, generating a design flow as a directed acyclic graph including the selected flowmodules as vertices; and generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules.

Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Abstract: An integrated circuit includes a first region corresponding to a first circuit and including a first dummy pattern and a first signal pattern which are spaced apart from each other by a width of a spacer in a conductive layer to extend in parallel in a first horizontal direction and a second region corresponding to a second circuit which is the same as the first circuit and including a second dummy pattern and a second signal pattern which are spaced apart from each other by the width of the spacer in the conductive layer to extend in parallel in the first horizontal direction. The first signal pattern and the second signal pattern are configured so that a first signal and a second signal corresponding to each other in the first circuit and the second circuit are respectively applied to the first signal pattern and the second signal pattern.