Patents Examined by Eric Jones
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Patent number: 9825077Abstract: A photoelectric conversion device includes a photoelectric conversion region having a plurality of photoelectric conversion elements and a first MOS transistor configured to read a signal in response to an electric charge of each photoelectric conversion element; and a peripheral circuit region having a second MOS transistor configured to drive the first MOS transistor and/or amplify the signal read from the photoelectric conversion region, the photoelectric conversion region and the peripheral circuit region being located on the same semiconductor substrate, wherein an impurity concentration in a drain of the first MOS transistor is lower than an impurity concentration in a drain of the second MOS transistor.Type: GrantFiled: July 22, 2015Date of Patent: November 21, 2017Assignee: Canon Kabushiki KaishaInventors: Takanori Watanabe, Tetsuya Itano, Hidekazu Takahashi, Shunsuke Takimoto, Kotaro Abukawa, Hiroaki Naruse, Shigeru Nishimura, Masatsugu Itahashi
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Patent number: 9761636Abstract: The inventive concepts relate to image sensors. The image sensor includes a substrate including a floating diffusion region and a pixel circuit, an interlayer insulating layer on the substrate, a contact node and a first electrode on the interlayer insulating layer, a dielectric layer on a top surface of the first electrode, a channel semiconductor pattern on the dielectric layer and connected to the contact node, and a photoelectric conversion layer on the channel semiconductor pattern. The channel semiconductor pattern includes a semiconductor material having an electron mobility that is higher than an electron mobility of the photoelectric conversion layer.Type: GrantFiled: June 5, 2015Date of Patent: September 12, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Yon Lee, Masaru Ishii
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Patent number: 9748290Abstract: Embodiments of mechanisms for forming an image sensor device structure are provided. The image sensor device structure includes a substrate and a transfer transistor formed on the substrate. The image sensor device structure also includes a floating node formed in the substrate and a photosensitive element formed in the substrate. The transfer transistor is formed between the floating node and the photosensitive element, and the photosensitive element includes a first doping region with a lateral doping gradient.Type: GrantFiled: February 3, 2014Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-Chuan Lee, Tzo-Hung Luo
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Patent number: 9734944Abstract: An inductive component is disclosed. The inductive component comprises a magnetic body and a coil in the magnetic body, wherein a first protrusion and a second protrusion are formed on the bottom surface of the magnetic body, wherein the first protrusion comprises a first electrode disposed on the peak surface of the first protrusion, and the second protrusion comprises a second electrode disposed on the peak surface of the second protrusion, wherein the first electrode and the second electrode are electrically connected to a first end and a second end of the coil, and a space is formed by the first protrusion, the second protrusion and the bottom surface of the magnetic body for accommodating electronic devices.Type: GrantFiled: November 4, 2014Date of Patent: August 15, 2017Assignee: CYNTEC Co., Ltd.Inventors: Bau-Ru Lu, Kai-Peng Chiang, Da-Jung Chen, Tsung-Chan Wu
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Patent number: 9735256Abstract: A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a first trench; etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature; depositing a dielectric material in the first trench and in the cavity; and etching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity.Type: GrantFiled: July 14, 2015Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Cheng Chang, Chih-Han Lin, Jr-Jung Lin, Shih-Hao Chen, Mu-Tsang Lin, Yung Jung Chang
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Patent number: 9721987Abstract: The semiconductor device includes a semiconductor substrate, an isolation feature, a photodiode and a transistor gate. The isolation feature is disposed in the semiconductor substrate. The photodiode is disposed in the semiconductor substrate and adjacent to the isolation feature. The photodiode includes a first pinned photodiode (PPD) with a first dopant type and a second PPD with a second dopant type. The second PPD is embedded in the first PPD, and is different from the first dopant type. The transistor gate is disposed over the photodiode and includes a first portion and a second portion. The first portion with the first dopant type is used for controlling the operation of the semiconductor device. The second portion with the second dopant type is adjacent to the first portion. The second portion covers the photodiode and extends toward the isolation feature.Type: GrantFiled: February 3, 2014Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yueh-Chuan Lee
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Patent number: 9711457Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.Type: GrantFiled: June 8, 2015Date of Patent: July 18, 2017Assignee: Micron Technology, Inc.Inventor: David S. Pratt
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Patent number: 9698225Abstract: A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.Type: GrantFiled: July 7, 2015Date of Patent: July 4, 2017Assignee: International Business Machines CorporationInventors: Effendi Leobandung, Tenko Yamashita
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Patent number: 9696464Abstract: The invention relates to a mold having an irregularly uneven surface structure in which an average inclination angle is from 20 to 80 degrees; an optical article having an irregularly uneven surface structure in which an average inclination angle is from 20 to 80 degrees; a method for manufacturing an optical article having an irregularly uneven surface structure by transferring an uneven structure of a mold; a transparent substrate for a surface light emitter which uses an optical article having an irregularly uneven surface structure; and a surface light emitter having a transparent substrate for a surface light emitter.Type: GrantFiled: June 15, 2012Date of Patent: July 4, 2017Assignee: Mitsubishi Rayon Co., Ltd.Inventors: Yumiko Saeki, Toshiaki Hattori, Toru Tokimitsu
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Patent number: 9698128Abstract: An LED module includes a substrate having a main surface and a rear surface located opposite the main surface, a main surface electrode located on the main surface, a plurality of penetration electrodes connected to the main surface electrode and extending through the substrate, three or more LED chips arranged on the main surface electrode along a first direction, and a case arranged on the main surface to surround the main surface electrode. The LED chips include at least one LED chip that can emit red light, at least one LED chip that can emit green light and at least one LED chip that can emit blue light.Type: GrantFiled: July 20, 2012Date of Patent: July 4, 2017Assignee: Rohm Co., Ltd.Inventors: Takashi Moriguchi, Masahiko Kobayakawa
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Patent number: 9646869Abstract: Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.Type: GrantFiled: March 2, 2010Date of Patent: May 9, 2017Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Ming Zhang
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Patent number: 9640398Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.Type: GrantFiled: May 14, 2015Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
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Patent number: 9627524Abstract: The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device).Type: GrantFiled: March 2, 2010Date of Patent: April 18, 2017Assignee: RICHTEK TECHNOLOGY CORPORATION, R.O.C.Inventors: Tsung-Yi Huang, Huan-Ping Chu, Ching-Yao Yang, Hung-Der Su
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Patent number: 9627552Abstract: A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum.Type: GrantFiled: July 31, 2007Date of Patent: April 18, 2017Assignee: VISHAY-SILICONIXInventor: Giovanni Richieri
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Patent number: 9620579Abstract: An organic light-emitting display apparatus includes a substrate; an active layer; a gate electrode, source and drain electrodes; a first insulating layer disposed between the active layer and the gate electrode; a second insulating layer disposed between the gate electrode and the source and drain electrodes; a third insulating layer disposed over the source and drain electrodes; conductive layers disposed over the third insulating layer and electrically connected to the source and drain electrodes through the third insulating layer; a first line disposed over the second insulating layer and formed of the same material as the source and drain electrodes; a second line overlapping the first line, disposed over the third insulating layer, and formed of the same material as the conductive layer; a fourth insulating layer disposed over the third insulating layer to cover the conductive layer; and an organic light-emitting diode disposed over the fourth insulating layer.Type: GrantFiled: August 25, 2015Date of Patent: April 11, 2017Assignee: Samsung Display Co., Ltd.Inventors: Nayoung Kim, Jungbae Kim
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Patent number: 9614190Abstract: A method for manufacturing a flexible display device includes forming a heat generator on a carrier substrate, forming a flexible substrate on the heat generator, forming a thin film transistor on the flexible substrate, forming a light emitting element connected to the thin film transistor, and separating the flexible substrate from the heat generator by application of heat to the flexible substrate, the application of heat including generation of heat by the heat generator.Type: GrantFiled: April 29, 2011Date of Patent: April 4, 2017Assignee: Samsung Display Co., Ltd.Inventors: Moo-Soon Ko, Il-Jeong Lee, Choong-Youl Im, Jong-Hyuk Lee, Sung-Chul Kim
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Patent number: 9608119Abstract: Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.Type: GrantFiled: March 2, 2010Date of Patent: March 28, 2017Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Ming Zhang, Andrew M. Bayless, John K. Zahurak
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Patent number: 9583400Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.Type: GrantFiled: January 15, 2016Date of Patent: February 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
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Patent number: 9543368Abstract: An OLED array substrate and a manufacturing method thereof, and a display device provided with the OLED array substrate are disclosed. The OLED array substrate includes a plurality of thin film transistors (2) disposed on a base substrate (1), each thin film transistor (2) being provided with a black matrix (6) thereon, and the black matrix (6) being provided with a via (60); over the black matrix (6) being disposed from bottom to top a first electrode (41), a luminescent layer (43) and a second electrode (42). The first electrode (41) is connected with the thin film transistor (2) through the via (60), and the first electrode (41) disposed over adjacent thin film transistors (2) are separated from each other by a barrier (44). The black matrix can block light emitted by the OLED to prevent TFTs from being illuminated, thereby ensuring the display effect of an active matrix type OLED display device.Type: GrantFiled: June 30, 2014Date of Patent: January 10, 2017Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Hongfei Cheng, Yuxin Zhang
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Patent number: 9541601Abstract: An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.Type: GrantFiled: July 20, 2012Date of Patent: January 10, 2017Assignee: STMICROELECTRONICS S.R.L.Inventor: Alberto Pagani