Abstract: The present disclosure provides novel light emitting devices including AMOLED displays, based on transparent OLED architecture, where a laminated nanostructured light extraction film can produce axial and integrated optical gains as well as improved angular luminance and color. Generally, the transparent AMOLED displays (100) with laminated sub-micron extractors (110a-c) include: (a) an extractor (110a) on a transparent substrate (112a) for light outcoupling on both sides of the transparent device (120); or (b) an extractor (110b) on a reflective film (112b) for providing light outcoupling off the bottom side of the bottom-emitting (BE) AMOLED (120); or (c) an extractor (110c) on a light absorbing film (112c) for providing outcoupling off the bottom side of the BE AMOLED (120) combined with improved ambient contrast.

Abstract: An organic layer deposition apparatus, and a method of manufacturing an organic light-emitting display device using the organic layer deposition apparatus. The organic layer deposition apparatus includes: an electrostatic chuck that fixedly supports a substrate that is a deposition target; a deposition unit including a chamber maintained at a vacuum and an organic layer deposition assembly for depositing an organic layer on the substrate fixedly supported by the electrostatic chuck; and a first conveyer unit for moving the electrostatic chuck fixedly supporting the substrate into the deposition unit, wherein the first conveyer unit passes through inside the chamber, and the first conveyer unit includes a guide unit having a receiving member for supporting the electrostatic chuck to be movable in a direction.

Abstract: A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum.

Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

Abstract: A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.

Abstract: Nanocrystalline diamond coatings exhibit stress in nano/micro-electro mechanical systems (MEMS). Doped nanocrstalline diamond coatings exhibit increased stress. A carbide forming metal coating reduces the in-plane stress. In addition, without any metal coating, simply growing UNCD or NCD with thickness in the range of 3-4 micron also reduces in-plane stress significantly. Such coatings can be used in MEMS applications.

Abstract: A semiconductor light-emitting element includes: a laminated semiconductor layer in which an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer are laminated; a transparent conductive layer laminated on the p-type semiconductor layer of the laminated semiconductor layer and composed of a metal oxide having optical transparency to light emitted from the light-emitting layer; an insulating reflation layer laminated on the transparent conductive layer in which plural opening portions are provided to expose part of the transparent conductive layer; a metal reflection layer formed on the insulating reflection layer and inside the opening portions and composed of a metal containing aluminum; and a metal contact layer provided between the part of the transparent conductive layer exposed at the opening portion and the part of the metal reflection layer formed inside the opening portion, which contains an element selected from Group VIA and Group VIII of a periodic table.

Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

Abstract: Variation in threshold voltages in a device operation is reduced. An insulator layer which is disposed to be opposed to a channel region 41 of a MOS transistor and is formed to have a laminated structure of a silicon nitride film 83 and a silicon oxide film 83 and an inverted signal input unit which inputs a signal obtained by inverting an input signal inputted into a source region 43 of a MOS transistor into a channel region 41 are provided and the inverted signal input unit includes another gate electrode 82 which is formed on an extended portion of the channel region 41 of the gate electrode 81 in a manner to be adjacent to the gate electrode 81 of the MOS transistor and a CMOS circuit 80 which inverts an input signal inputted into the source region 43 of the MOS transistor in accordance with an input value of the input signal and inputs a signal obtained through inversion in the CMOS circuit 80 into another gate electrode 82.

Abstract: Embodiments of the present invention disclose an array substrate comprising a plurality of pixel units disposed on a base substrate, the pixel units comprising: a thin film transistor structure formed on the base substrate; and an OLED driven by the thin film transistor structure, the OLED disposed in a pixel region of the pixel units, the OLED comprising sequentially in a direction away from the base substrate a first electrode which is transparent, a light-emitting layer and a second electrode which reflects light; a transflective layer disposed between the OLED and the thin film transistor structure; a color filter disposed between the second electrode of the OLED and the transflective layer; the second electrode of the OLED and the transflective layer constitute a microcavity structure.

Abstract: Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as SRAM design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (Vt) for a part of the fin, rendering that part of the fin electrically inactive, which changes the effective device width (Weff). Other fins are unclad, and provide maximum area of constant threshold voltage. In this way, the effective device width of some devices is reduced. Therefore, the effective device width is controllable by controlling the level of cladding of the fin.

Abstract: An organic light-emitting display apparatus includes a capping layer above an organic emission layer, an encapsulating layer encapsulating the capping layer and the organic emission layer, and a deposition layer above the capping layer and below the encapsulating layer, the deposition layer including a surface on which a plurality of cylinders are located.

Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.

Abstract: Provided is a diode element, a detecting device, and the like which solve problems of a conventional lateral diode element. In the conventional element, a semiconductor interface appears in current path between two electrodes on a surface thereof, and thus noise caused by the interface is large. The diode element includes: a first-conductive-type low carrier concentration layer; a first-conductive-type high carrier concentration layer; and a Schottky electrode and an ohmic electrode which are formed on a semiconductor surface. The low carrier layer has a carrier concentration that is lower than that of the high carrier layer. The diode element includes a first-conductive-type impurity introducing region formed below the ohmic electrode, and includes a second-conductive-type impurity introducing region so as not to be in electrical contact with the Schottky electrode on the semiconductor surface between the Schottky and the ohmic.

Abstract: Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor.

Abstract: The present invention relates to light emitting diodes comprising at least one nanowire. The LED according to the invention is an upstanding nanostructure with the nanowire protruding from a substrate. A bulb with a larger diameter than the nanowire is arranged in connection to the nanowire and at an elevated position with regards to the substrate. A pn-junction is formed by the combination of the bulb and the nanowire resulting in an active region to produce light.

Abstract: A method for forming a semiconductor device includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. A thickness of the first portion of the dielectric layer is adjusted by either reducing the thickness or depositing additional dielectric material. A capacitor top plate is formed over the first portion of the dielectric layer.

Abstract: Provision of a super-junction semiconductor device capable of reducing rises in transient on-resistance at the time of repeated switching operation. A super-junction structure is provided that has a striped parallel surface pattern, where a super-junction stripe and a MOS cell 6 stripe are parallel, and a p column Y2 over which no MOS cell 6 stripe is arranged and a p column Y1 over which the MOS cell 6 stripe is arranged are connected at an end.

Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.

Abstract: A biocompatible electrode is manufactured by depositing filling metal 36 and etching back the filling metal to the surface of the surrounding insulator 30. Then, a further etch forms a recess 38 at the top of the via 32. An electrode metal 40 is then deposited and etched back to fill the recess 38 and form biocompatible electrode 42. In this way, a planar biocompatible electrode is achieved. The step of etching to form the recess may be carried out in the same CMP tool as is used to etch back the filling metal 36. A hydrogen peroxide etch may be used.