Abstract: Method and apparatus for archiving de-duplicated data maintained by an intelligent backup appliance are described. In some examples, backup data managed by a backup appliance in a computer system is archived. A request to archive selected backup images of a plurality of backup images maintained by the backup appliance is received. The selected backup images are compared with a pool of de-duplicated data for the plurality of backup images maintained by the backup appliance to identify common data among the selected backup images and unique data in each of the selected backup images. A core backup is stored on first archive storage media, the core backup including at least a portion of the common data. A unique backup is stored on second archive storage media, the unique backup including the unique data a reference to the core backup stored on the first archive storage media.

Abstract: A computerized method for dynamic consistency management of server side cache management units in a distributed cache, comprising: updating a server side cache management unit by a client; assigning each of a plurality of server side cache management units to one of a plurality of propagation topology groups according to an analysis of a plurality of cache usage measurements thereof, each of said propagation topology groups is associated with a different write request propagation scheme; and managing client update notifications of members of each of said propagation topology groups according to the respective said different write request propagation scheme which is associated therewith.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: Example embodiments provide access to an updated file performed by at least one processor, wherein responsive to receiving a first list of logical page numbers (LPNs) and a second list of LPNs for an update, wherein the first list of LPNs is mapped to a first list of physical page numbers (PPNs), and the second list of LPNs is mapped to a second list of PPNs, the method, comprising: atomically remapping the first list of LPNs so that the first list of LPNs is mapped to the second list of PPNs; and trimming a mapping of the first list of LPNs to the first list of PPNs.

Abstract: Exemplary embodiments provide access to an updated file performed by at least one processor, wherein responsive to receiving a first list of logical block addresses (LBAs) and a second list of LBAs for an update, wherein the first list of LBAs is mapped to a first list of physical block addresses (PBAs), and the second list of LBAs is mapped to a second list of PBAs, the method, comprising: atomically remapping the first list of LBAs so that the first list of LBAs is mapped to the second list of PBAs; trimming a mapping of the first list of LBAs to the first list of PBAs; and unmapping the mapping of the second list of LBAs to the second list of PBAs.

Abstract: Exemplary embodiments provide access to an updated file performed by a computer having at least one processor, wherein responsive to an application receiving an update comprising modified content of an old file, a new file is created into which the modified content is copied, while access to the old file is maintained, wherein old file logical block addresses (LBAs) are mapped to old file physical block addresses (PBAs), and new file LBAs are mapped to new file PBAs, the method, comprising: atomically swapping the mapping of the old file LBAs from the old file PBAs to the new file PBAs; trimming the mapping of the old file LBAs to the old file PBAs; and clearing the mapping of the new file LBAs to the new file PBAs.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: In conventional unified storage systems, an I/O for block storage and an I/O for file storage are processed in a single OS without being distinguished, so that it was not possible to perform processes for speedy failure detection or for enhancing performances such as tuning of performance by directly monitoring hardware. The present invention solves the problem by having a block storage-side OS and an OS group managing multiple systems including a file system other than the block storage-side OS coexist within a storage system, wherein the OS group managing multiple systems including a file system other than the block storage-side OS is virtualized by a hypervisor, wherein a block storage micro-controller and the hypervisor can cooperate in performing processes.

Abstract: Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of bytes that include an instruction may be read from an instruction cache based on a logical instruction pointer. A determination is made whether a first byte of the plurality of bytes identifies a length of the instruction. In response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, the instruction is read from the plurality of bytes based on the length of the instruction.

Abstract: According to the disclosure, a unique and novel archiving system that allows the digital shredding of archived data is disclosed. Embodiments of the archiving system include removable disk drives that store data, which may be erased such that the data is considered destroyed but that allows the removable disk drive to be reused. The archiving system can determine which data should be erased. Then, the data is digitally shredded such that the removed data cannot be retrieved or deciphered. In alternative embodiments, a protection may be placed on the data required to be kept because the data is associated with a legal suit. This “legal hold” prevents the data from being digitally shredded. As such, the archiving system can provide a system that can dispose of data on a file-by-file or granular level without physically destroying the media upon which the data is stored.

Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.

Abstract: Techniques are provided for performing OID-to-VMA translations during runtime. Vector registers are used to implement a “software TLB” to perform OID-to-VMA translations. Runtime dereferencing is performed using one or more vector registers to compare each OID that needs to be dereferenced against a set of cached OIDs. When a cached OID matches the OID being dereferenced, the VMA of the cached OID is retrieved from cache. Buffer cache items may be pinned during the period in which the software TLB stores entries for the items. The cache of OID translation information may be single or multi-leveled, and may be partially or completely stored in registers within a processor. When stored in registers, the translation information may be spilled out of the register, and reloaded into the register, as the register is needed for other purposes.

Abstract: A method begins by a processing module identifying a first storage space zone that includes a plurality of deleted encoded data slices and a plurality of active encoded data slices. The method continues with the processing module determining to compact the first storage space zone based on a function of the plurality of deleted encoded data slices and the plurality of active encoded data slices. The method continues with the processing module retrieving the plurality of active encoded data slices from the first storage space zone, identifying a second storage space zone, storing the plurality of active encoded data slices in the second storage space zone, and erasing the plurality of deleted encoded data slices and the plurality of active encoded data slices from the first storage space zone when the first storage space zone is to be compacted.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Abstract: Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete.

Abstract: A memory device and method for content virtualization are disclosed. In one embodiment, a plurality of directories are created in the memory of the memory device, wherein each of the plurality of directories points to a same storage location of the digital content. In another embodiment, a first header for the digital content is stored in each of the different directories, wherein the first header comprises information about where to find the digital content in the memory. In yet another embodiment, the memory device comprises circuitry that receives an identification of a host device in communication with the memory device and reorganizes a directory structure of the memory in accordance with the identification of the host device, wherein the reorganization results in the digital content appearing to be located in a directory expected by the host device.

Abstract: A memory device and method for content virtualization are disclosed. In one embodiment, a plurality of directories are created in the memory of the memory device, wherein each of the plurality of directories points to a same storage location of the digital content. In another embodiment, a first header for the digital content is stored in each of the different directories, wherein the first header comprises information about where to find the digital content in the memory. In yet another embodiment, the memory device comprises circuitry that receives an identification of a host device in communication with the memory device and reorganizes a directory structure of the memory in accordance with the identification of the host device, wherein the reorganization results in the digital content appearing to be located in a directory expected by the host device.

Abstract: A system, method, and computer-readable medium that facilitate efficient use of cache memory in a massively parallel processing system are provided. A residency time of a data block to be stored in cache memory or a disk drive is estimated. A metric is calculated for the data block as a function of the residency time. The metric may further be calculated as a function of the data block size. One or more data blocks stored in cache memory are evaluated by comparing a respective metric of the one or more data blocks with the metric of the data block to be stored. A determination is then made to either store the data block on the disk drive or flush the one or more data blocks from the cache memory and store the data block in the cache memory. In this manner, the cache memory may be more efficiently utilized by storing smaller data blocks with lesser residency times by flushing larger data blocks with significant residency times from the cache memory.

Abstract: In conventional unified storage systems, an I/O for block storage and an I/O for file storage are processed in a single OS without being distinguished, so that it was not possible to perform processes for speedy failure detection or for enhancing performances such as tuning of performance by directly monitoring hardware. The present invention solves the problem by having a block storage-side OS and an OS group managing multiple systems including a file system other than the block storage-side OS coexist within a storage system, wherein the OS group managing multiple systems including a file system other than the block storage-side OS is virtualized by a hypervisor, wherein a block storage micro-controller and the hypervisor can cooperate in performing processes.