Abstract: A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Abstract: An exact match lookup system includes a hash function that generates a hash value in response to an input hash key. The hash value is used to retrieve a hash bucket index value from a hash bucket index table. The hash bucket index value is used to retrieve a plurality of hash keys from a plurality of hash bucket tables, in parallel. The retrieved hash keys are compared with the input hash key to identify a match. Hit logic generates an output index by concatenating the hash bucket index value with an address associated with the hash bucket table that provides the matching hash key. An exact match result is provided in response to the output index. A content addressable memory (CAM) may store hash keys that do not fit in the hash bucket tables.

Abstract: A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

Abstract: A memory managing method is provided for a memory system, including a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory managing method includes determining whether a program-erase number of a memory block in the nonvolatile memory device reaches a first reference value; managing a life of the memory block according to a first memory managing method when the program-erase number of the memory block is determined to be less than the first reference value; and managing the life of the memory block according to a second memory managing method different from the first memory managing method when the program-erase number of the memory block is determined to be greater than the first reference value.

Abstract: Examples disclose partitioning a volatile memory into a high performance partition and a low performance partition. Further the example discloses retrieving an application with a high performance data and a low performance data from a non-volatile memory to place the high and the low performance data in the high and low performance partitions, respectively. Additionally, the example also discloses receiving a request to decrease power and in response, reduce an amount of power to the high performance partition and maintaining an amount of power provided to the low performance partition.

Abstract: A multiport memory having an array of storage cells for storing data; a plurality of data access ports; and access control circuitry to assign each data access port to one of the sets of access control lines and corresponding data lines. The control circuitry has collision detection circuitry to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port. The control circuitry is responsive to the detected collision to assign the set of access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and to subsequently assign the first data access port to the set of access control lines and corresponding data lines previously assigned to the second access port.

Abstract: A system and method are disclosed for determining whether to allow or deny an access request based upon one or more descriptors at a local memory protection unit and based upon one or more descriptors a system memory protection unit. When multiple descriptors of a memory protection unit apply to a particular request, the least-restrictive descriptor will be selected. System access information is stored at a cache of a local core in response to a cache line being filled. The cached system access information is merged with local access information, wherein the most-restrictive access is selected.

Abstract: Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

Abstract: An I/O request to store a file in a file-system is received. A determination is made whether the size of the file does not exceed a threshold size. Exceeding the threshold results in storing at least a portion of the file in a block of the file-system devoid of sub-blocks. A determination is made whether the size of the file does not exceed a size of unallocated space within a single block in the file-system. The single block includes a set of sub-blocks. Responsive to the size of the file not exceeding the threshold size and the size of unallocated space within the single block, the file is stored, at an address, in a first subset of the set of the sub-blocks of the single block. The address identifies the single block and a position of a sub-block in the subset.

Abstract: A system that implements a scalable data storage service may maintain tables in a data store on behalf of storage service clients. The service may maintain table data in multiple replicas of partitions that are stored on respective computing nodes in the system. In response to detecting an anomaly in the system, detecting a change in data volume on a partition or service request traffic directed to a partition, or receiving a service request from a client to split a partition, the data storage service may create additional copies of a partition replica using a physical copy mechanism. The data storage service may issue a split command defined in an API for the data store to divide the original and additional replicas into multiple replica groups, and to configure each replica group to maintain a respective portion of the table data that was stored in the partition before the split.

Abstract: Dynamically creating a communication path between first and second storage devices, includes creating a connection to a source volume on the first storage device and indicating that the source volume is not ready to transmit data on the communication path, after successfully creating the connection to the source volume, creating a connection to a destination volume on the second storage device and initially indicating that portions of one of: the destination volume and the source volume do not contain valid copies of data, where the destination volume accepts data from the source volume, and after successfully creating the connections to the source and destination volumes, indicating that the source volume is ready to transmit data on the communication path. Dynamically creating a communication path between first and second storage devices, may also include creating at least one of: the source volume and the destination volume.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: At least one virtual machine implemented on a given physical machine in an information processing system is able to detect the presence of one or more other virtual machines that are also co-resident on that same physical machine. More particularly, at least one virtual machine is configured to avoid usage of a selected portion of a memory resource of the physical machine for a period of time, and to monitor the selected portion of the memory resource for activity during the period of time. Detection of a sufficient level of such activity indicates that the physical machine is also being shared by at least one other virtual machine. The memory resource of the physical machine may comprise, for example, a cache memory, and the selected portion of the memory resource may comprise one or more randomly selected sets of the cache memory.

Abstract: In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.

Abstract: A data block storage management capability is presented. A file system includes a plurality of data blocks which are managed using a first storage service and a second storage service, where the first storage service has a lower storage cost and a higher input-output cost than the second storage service. The data blocks stored using the second storage service have associated therewith respective expected storage durations indicative of respective lengths of time for which the data blocks are to be stored using the second storage service (which may be the same or different across the ones of the data blocks stored using the second storage service). The expected storage durations of the data blocks are modified based on a comparison of an expected hit rate of the second storage service and a current hit rate of the second storage service or current hit rates of the data blocks.

Abstract: The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring whether some of the blocks arranged in the same set of the cache memory have been modified in contents, and a cache block replacing unit for replacing a block, which has not been modified in contents, if some of the blocks arranged in the same set have been modified in contents.

Abstract: The techniques introduced here provide for efficient management of storage resources in a modern, dynamic data center through the use of virtual storage appliances. Virtual storage appliances perform storage operations and execute in or as a virtual machine on a hypervisor. A storage management system monitors a storage system to determine whether the storage system is satisfying a service level objective for an application. The storage management system then manages (e.g., instantiates, shuts down, or reconfigures) a virtual storage appliance on a physical server. The virtual storage appliance uses resources of the physical server to meet the storage related needs of the application that the storage system cannot provide. This automatic and dynamic management of virtual storage appliances by the storage management system allows storage systems to quickly react to changing storage needs of applications without requiring expensive excess storage capacity.

Abstract: Methods and apparatuses for improving security of an integrated circuit (IC) are provided. A tamper condition is detected and a digital key stored in the IC is erased. The digital key is associated with a first image loaded onto the IC from a first memory. The memory may be a non-volatile memory module. A second image is loaded into a second memory module. The second memory module may be an embedded memory module, e.g., a control random access memory (CRAM) module. The first image is then erased from the first and second memory modules.

Abstract: A system, computer readable program, and method for programming flash memory, the method includes: providing multiple pairs of most significant bit (MSB) page uncoded bit error rates (UBERs) and least significant bit (LSB) page UBERs; selecting a selected MSB page code rate and a selected LSB page code rate so that a selected MSB page UBER associated with the selected MSB page code rate and a selected LSB page UBER associated with the selected LSB page code rate support a highest average UBER out of the multiple pairs of MSB page UBERs and LSB page UBERs, wherein the selected MSB page code rate and the selected LSB page code rate are obtainable under a desired code rate constraint; and determining an encoding and programming scheme that may be based on the selected MSB page UBER, the selected MSB code rate, the selected LSB page UBER and the selected LSB code rate.

Abstract: Embodiments of the present invention provide a virtualization protection system (VPS) that leverages virtual machine monitor (VMM) technology. In some embodiments, a computer system contains a host operating system and one or more virtual machines that run on “guest” operating systems. The VPS makes certain areas of memory of the computer system read-only, making it essentially impossible for the virtual machines or other component to compromise the system.