Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: Memory is serviced. In response to an input indicating a serious condition, a service is invoked that is unaffected by the serious condition. By the service, it is determined whether other instructions are available to be executed that are not being affected by the serious condition. By the other instructions, data is copied from a write cache to a nonvolatile memory before the data is lost from the write cache.

Abstract: Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.

Abstract: A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.

Abstract: An apparatus for managing memory in a real-time embedded system and a method of allocating, deallocating and managing memory in a real-time embedded system. The apparatus includes a defragmentation unit performing a defragmentation task according to a predetermined priority to collect together memory fragments, and a memory manager allocating or deallocating a predetermined area of memory upon request of a task, and calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task. The method of managing memory in a real-time embedded system includes determining whether the conditions under which the memory is used vary, and if the condition vary, calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task according to the memory fragmentation rate.

Abstract: An information processor includes a rotating magnetic disk that stores therein data, an accessing unit that accesses the magnetic disk, a detecting unit that detects an abnormal state. The abnormal state is a state that a user takes an action that may cause the magnetic disk to vibrate. The information processor further includes a control unit that terminates an access to the magnetic disk and stops rotation of the magnetic disk when the detecting unit detects the abnormal state, and an output unit that outputs a request for the action after the control unit has stopped the access and the rotation.

Abstract: Concepts for enhancing operation of transaction-safe file allocation table systems are described. The concepts include writing a file to non-volatile memory media and rendering an update of file size to the TFAT storage medium; and receiving a request to locate data in a non-volatile memory having a TFAT file management system, selecting a sector of the memory to parse to locate the data, determining when the selected sector is a first sector of a directory or subdirectory of the memory and when determining reveals that the selected sector is a first sector, skipping reading data from the selected sector. The concepts also include flushing a cache and synchronizing FATs.

Abstract: In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag responsive to an index corresponding to an input address. The comparator is coupled to receive the tag and a tag portion of the input address, and is configured to compare the tag to the tag portion to generate a hit/miss indication. The comparator comprises dynamic circuitry, and is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion matches the tag. The comparator also comprises circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result responsive to an assertion of the control signal.

Abstract: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Abstract: A method of controlling copying of an information signal, comprises the steps of: prior to recordal and/or transmission, applying to the information signal a substantially imperceptible modification representing copy control data including a password securely encoded according to a predetermined algorithm; upon reproduction for copying by a user, deriving (S1, S3) the copy control data from the modified information signal; comparing (S8, S9, S11, S13, S15) the derived securely encoded password with a reference password securely encoded according to a predetermined algorithm; and enabling (S5) copying of the information signal if the securely encoded password derived from the information signal and the securely encoded reference password have a predetermined relationship, otherwise disabling copying (S7). The reference password is sent to the user via a channel which is separate from a channel used to send the information signal to the user.

Abstract: A storage controller of the present invention can input and output data even when the track size, which is the host management unit, is not consistent with the block size of the storage device. A boundary correction unit adds gap data corresponding to a gap size to data in a buffer memory so that the boundary of the track and boundary of the block inside the storage device match. A guarantee code is added to each logical block received from the host, and these guarantee code-appended blocks are stored in a cache memory. By providing a gap in the storage device every 116 extended logical blocks, the start position of the lead block of a track matches up with the start position of the logical blocks of the storage device.

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

Abstract: A computer system wherein, when a state of the primary host computer is in an active state, a data sent from the primary host computer to the first storage system is copied through a first copy route which includes a route from the first storage system to the second storage system and a route from the second storage system to the third storage system, wherein, if a failure occurs in the primary host computer and a state of the second host computer is to be in an active state, a data sent from the secondary host computer to the second storage system is copied through a second copy route which includes a route from the second storage system to the first storage system and a route from the first storage system to the third storage system.

Abstract: In one embodiment, the present invention includes a virtual machine monitor (VMM) to access a protection indicator of a page table entry (PTE) of a page of a set of memory buffers and determine a state of the protection indicator, and if the protection indicator indicates that the page is a user-level page and if certain information of an agent that seeks to use the page matches that in a protected memory address array, a page table base register (PTBR) is updated to a protected page table (PPT) base address. Other embodiments are described and claimed.

Abstract: A semiconductor memory card that has a sufficient storage capacity when an EC application writes data to a storage is provided. A usage area for the EC application in an EEPROM 3 in a TRM 1 is expanded. The expansion is such that a partition generated in a flash memory 2 outside the TRM 1 is assigned to the EC application while a partition table is allocated in the internal EEPROM 3. Because the partition table is in the TRM 1, only a CPU 7 in the TRM 1 is able to access the generated partition table. Secrecy of stored contents increases because the access to the expanded area is limited to the CPU 7 in the TRM 1.

Abstract: A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.

Abstract: A method of memory management is disclosed. The invention increases bank diversity by splitting requests and is also integrated with re-ordering and priority arbitration mechanisms. Therefore, the probabilities of both bank conflicts and write-to-read turnaround conflicts are reduced significantly, so as to increase memory efficiency.

Abstract: An improved system and method enhances performance of updates to sequential block storage of a storage system. A disk-based sort procedure is provided to establish locality among updates (write data) held in a disk-based log, thereby enabling the write data to be efficiently written to home locations on a home location array. As the write data is received, a log manager of the storage system temporarily stores the data efficiently on the disk-based log. As more write data arrives, the log manager sorts the data in the log in accordance with the sort procedure, thus increasing the locality of data when stored on the home location array. When the log approaches capacity, the log manager writes the sorted data to their home locations on the array with high locality and performance.

Abstract: Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.