Abstract: Access to data storage is enhanced. A logical volume defines a set of block based data storage resources and is presented as a first volume. A virtual LUN portal mechanism serves as an alias for the first volume and is presented as a second volume. A block based data manipulation mechanism is configured to apply to a first I/O request directed to the second volume and not to a second I/O request directed to the first volume.

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

Abstract: A method for writing data to a RAID 5 configuration of hard disks writes two or more items of data to a data stripe together. The method includes the determining of the suitability of data items to be written together, the storing of the new data items to temporary buffers, the reading of the original data and parity from the hard disk to the temporary buffers, the modification of the parity and the writing of the new data and new parity to the hard disks.

Abstract: A flash storage chip including a single circuit board, a microcontroller, a flash memory, and a peripheral component interconnect express (PCI Express) connecting interface is provided. The microcontroller, the flash memory, and the PCI Express connecting interface are embedded on the single circuit board, and the microcontroller has a flash memory interface and a PCI Express interface. When a host writes a data into the flash storage chip, the microcontroller receives the data though the PCI Express interface and stores the data into the flash memory though the flash memory interface. When the host reads a data form the flash storage chip, the microcontroller reads the data from the flash memory though the flash memory interface and transmits the data to the host though the PCI Express interface and the PCI Express connecting interface.

Abstract: In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

Abstract: Object-based conflict detection is described in the context of software transactional memory. In one example, a pointer is received for a block of instructions, the block of instructions having allocated objects. The lower bits of the pointer are masked if the pointer is in a small object space to obtain a block header for the block, and a size of the allocated objects is determined using the block header.

Abstract: Intelligent allocation of programmable comparison operations may reduce the number of associative memory entries required for programming an associative memory (e.g., ternary content-addressable memory) with multiple matching definitions (e.g., access control list entries, routing information, etc.), which may be particularly useful in identifying packet processing operations to be performed on packets in a packet switching device. The higher-cost comparison operations, in terms of the number of associative memory entries required to natively support such operations, are allocated to one or more comparison evaluators (e.g., programmable logic and/or processing elements configured to evaluate one or more comparison operations) configured to evaluate an input value with one or more of the programmable comparison operations in order to generate and provide one or more values representing results of the evaluations to one or more associative memories for use in identifying the packet processing operations.

Abstract: A storage device that includes: a flash memory device being a main storage medium; a cache memory for use for the flash memory device; and a control circuit. In the storage device, based on a write command and address information provided from outside, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.

Abstract: Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. To prevent erasure of the stored information when power to the FPGA is removed, or when the FPGA is configured, or when applications are installed, a battery powers the memory. The battery power may be interrupted, for example if a tamper is detected, in order to erase the contents of the memory. Access to data stored in memory may also be limited by using authorization codes or encryption. For example, an application may only be granted access if it provides the correct authorization code. Alternately, an application may encrypt data with a key before it is stored. Only an application with the correct key can make further use of the data.

Abstract: Disclosed is a method and apparatus for crossbar arbitration. In one embodiment, the crossbar arbitration includes a memory, a plurality of functional units that transfer data to and from the memory, a crossbar unit that provides a data path from each unit to the memory, and an arbitration unit that monitors data traffic generated by each functional unit through the crossbar unit and assigns a priority to each functional unit based on the data traffic. In another embodiment, the crossbar arbitration includes a method for data transfer arbitration including monitoring data transfers for a plurality of devices, and assigning a priority to each device corresponding to the amount of data transfers generated by the device.

Abstract: A memory device includes two dies. A first memory is fabricated on one die. A controller of the first memory is fabricated on the other die. Also fabricated on the other die is another component, such as a second memory, that communicates with a host system using a plurality of signals different from the signals used by the first memory. The device includes a single interface for communicating with the host system using only the respective signals of the second component. In a most preferred embodiment, the first memory is a NAND flash memory and the second memory is a SDRAM.

Abstract: Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.

Abstract: Interfaces for flexible storage management. An embodiment of a system includes a data storage, the data storage including one or more of a first storage system, the first storage system including a file structure that is coextensive with a set of memory devices, or a second storage system, the second storage system including a storage structure that is coextensive with a set of memory devices, the storage structure including zero or more file structures. The system further includes an interface system for the data storage, the interface system being used for both the first storage system and the second storage system.

Abstract: Memory parameters are controlled. A power source capacity estimate is determined. Based on the power source capacity estimate, an amount of cache to enable is determined and is enabled.

Abstract: The present invention includes means for processing received data, storage means for storing the data, means for performing an invalidation process on the data stored in the storage means, and means for storing history information about the history of the invalidation process performed.

Abstract: A memory address monitoring device for monitoring a memory includes an address determining module and an identification determining module. A first process has a first process identification and issues a request address to access the memory. The memory saves data of a second process between a beginning address and an ending address of the memory. The second process has a second process identification. In this device, the address determining module receives the request address and determines whether the request address is located between the beginning address and the ending address to generate an address determining result. The identification determining module receives the address determining result, the first process identification and the second process identification, and compares the first process identification with the second process identification to generate an identification determining result when the address determining result is true.

Abstract: A topology independent storage array. In a preferred embodiment the topology of the array is reconfigurable due to information control packets passed among storage nodes comprising the array. The topology of the array, as determine by the relationship between data sets stored within the array's storage nodes and storage maps of the storage node, can be reconfigured without requiring a complete duplication of the entire array. In especially preferred embodiments, the topology of the storage array follows a Z-10 or a Z-110 configuration where storage devices store one or more mirrored parts of a data set per storage device.

Abstract: System for controlling data transfer between a host system and storage devices. A virtualization controller implements the data transfer and includes first ports for connection with the storage devices, a second port for connection with the host system, a processor, and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area. When data stored in the first storage area is transferred to a second storage area, the processor correlates the first identification information with a third identification information for identifying the second storage area and registers the first identification information and the third identification information in the volume mapping information.

Abstract: A storage network system that can be kept running despite a failure in a host computer is provided. A computer system includes: first, second and third storage systems which store data and are connected to one another; a primary host computer connected to the first storage system; a secondary host computer connected to the second storage system; and a management portion which manages data transfer between the storage systems, in which the management portion sets the storage systems such that, while the primary host computer is in operation, data stored in the first storage system is transferred to the second storage system and data stored in the second storage system is transferred to the third storage system, and wherein the management portion sets the storage systems such that, while the secondary host computer is in operation, data stored in the second storage system is transferred to the first storage system and data stored in the first storage system is transferred to the third storage system.

Abstract: Systems, methods and media for performing auto-migration of data among a plurality of memory devices are disclosed. In one embodiment, memory access of application program data is monitored for each of one or more application programs. The data may be stored in one or more of a plurality of memory storage devices, each with its own performance characteristics. Monitored access is evaluated to determine an optimal distribution of the application programs data, typically stored in files, among the plurality of memory storage devices. The evaluation takes into account service level requirements of each application program. Periodically, data may be automatically transferred from one memory storage device to another to achieve the determined optimal allocation among the available memory storage devices consistent with service level requirements.