Patents Examined by Eric T Oberly
  • Patent number: 12013799
    Abstract: Systems and methods for memory management for guests. An example method may include running, by a host computer system, a host component managing a guest in communication with a peripheral device, wherein the peripheral device comprises an input/output memory management unit (IOMMU). The method may further include appending, to a page table of the IOMMU, a plurality of records referencing present memory pages associated with a task running on the guest and appending, to the page table of the IOMMU, a plurality of records referencing read-only memory pages associated with the task, wherein the read-only memory pages are indicated as read-only in the page table.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: June 18, 2024
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, David Gilbert
  • Patent number: 12014045
    Abstract: Systems and methods for sampling a set of block IDs to facilitate estimating an amount of data stored in a data set of a storage system having one or more characteristics are provided. According to an example, metadata (e.g., block headers and block IDs) may be maintained regarding multiple data blocks of the data set. When one or more metrics relating to the data set are desired, an efficiency set, representing a subset of the block IDs of the data set, may be created to facilitate efficient calculation of the metrics by sampling the block IDs of the data set. Finally, the metrics may be estimated based on the efficiency set by analyzing one or more of the metadata (e.g., block headers) and the data contained in the data blocks corresponding to the subset of the block IDs and extrapolating the metrics for the entirety of the data set.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: June 18, 2024
    Assignee: NetApp, Inc.
    Inventors: Charles Randall, Alyssa Proulx
  • Patent number: 12007931
    Abstract: A bus system of the disclosure includes three or more devices that include one or a plurality of imaging devices, and transmit or receive data signals in a time-division manner; and a bus to which the three or more devices are coupled.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 11, 2024
    Assignee: Sony Group Corporation
    Inventors: Hideyuki Matsumoto, Hiroaki Hayashi, Takashi Yokokawa, Naoki Yoshimochi
  • Patent number: 12001338
    Abstract: Disclosed is an approach for implementing a metadata cache in a virtualization system. A self-adaptive approach is provided to keep compressed and uncompressed entries together in cache. Along with adaptive nature, disclosed is an approach to prioritize critical workloads for the cache.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: June 4, 2024
    Assignee: Nutanix, Inc.
    Inventors: Gaurav Jain, Rohit Ghivdonde, Srihita Goli, Shyam Sankaran, Anoop Jawahar
  • Patent number: 12001711
    Abstract: The present disclosure generally relates to utilizing the host clock signal frequency to determine whether to operate in the default pulse width modulation (PWM) link startup sequence (LSS), be changed to high speed (HS) LSS by a host device capable of operating in either PWM LSS or HS LSS, or ignore the data storage device attributes of operating in PWM LSS and instead operate according to HS LSS. In so doing, the data storage device is adaptable to work with older generation UFS host devices as well as current and future generation UFS host devices.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 4, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Shemmer Choresh
  • Patent number: 11995019
    Abstract: A peripheral component interconnect express (PCIe) device includes a plurality of common functions performing operations associated with a PCIe interface according to a function type of each of the plurality of common functions, each of the plurality of common functions being programmable to be a function type selected from a plurality function types, and a function type controller determining the function type of each of the plurality of common functions based on function type setting information provided from a host. Each function type may be a physical function type, a virtual function type, or a disable function type.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: May 28, 2024
    Assignee: SK hynix Inc.
    Inventors: Yong Tae Jeon, Byung Cheol Kang, Seung Duk Cho
  • Patent number: 11995024
    Abstract: Some embodiments provide a method for synchronizing state between multiple smart NICs of a host computer that perform operations using dynamic state information. At a first smart NIC of the plurality of smart NICs, the method stores a set of dynamic state information. The method synchronizes the set of dynamic state information across a communication channel that connects the smart NICs so that each of the smart NICs also stores the set of dynamic state information.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 28, 2024
    Assignee: VMware LLC
    Inventors: Boon S. Ang, Wenyi Jiang, Guolin Yang, Jin Heo
  • Patent number: 11991072
    Abstract: A network interface controller (NIC) capable of efficient event management is provided. The NIC can be equipped with a host interface, a first memory device, and an event management module. During operation, the host interface can couple the NIC to a host device. The event management module can identify an event associated with an event queue stored in a second memory device of the host device. The event management module can insert, into a buffer, an event notification associated with the event. The buffer can be associated with the event queue and stored in the first memory device. If the buffer has met a release criterion, the event management module can insert, via the host interface, the aggregated event notifications into the event queue.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 21, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Duncan Roweth, Edwin L. Froese
  • Patent number: 11972149
    Abstract: A storage system is provided that performs a defragmentation operation or proactive garbage collection in its memory based on a command from a host. The command specifies which blocks in the memory should take part in the defragmentation operation by specifying a maximum amount of valid data that a block can have to qualify for defragmentation. That way, the storage system only performs defragmentation on those blocks that meet the validity criteria provided by the host. This can help improve performance of the storage system while reducing the degree of negative tradeoffs that may come with defragmentation or proactive garbage collection.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Nadav Sober, Omer Katz
  • Patent number: 11973655
    Abstract: Some embodiments provide a method of performing control plane operations in a radio access network (RAN). The method deploys several machines on a host computer. On each machine, the method deploys a control plane application to perform a control plane operation. The method also configures on each machine a RAN intelligent controller (RIC) SDK to serve as an interface between the control plane application on the same machine and a set of one or more elements of the RAN. In some embodiments, the RIC SDK on each machine includes a set of network connectivity processes that establish network connections to the set of RAN elements for the control plane application. These RIC SDK processes allow the control plane application on their machine to forego having the set of network connectivity processes.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: April 30, 2024
    Assignee: VMware LLC
    Inventors: Aditya Gudipati, Amit Singh
  • Patent number: 11966587
    Abstract: A method for optimizing a Polar-RNNA quantizer of MLC NAND flash based on deep learning comprises the following steps: Step S1: transforming an MLC flash detection task into a deep learning task, and obtaining three hard-decision read thresholds based on a neural network; Step S2: expanding six soft-decision read thresholds based on the three hard-decision read thresholds; Step S3: constructing an LLR mapping table, and obtaining new LLR information of MLC flash based on the LLR mapping table; Step S4: symmetrizing an MLC flash channel, and performing density evolution; and Step S5: optimizing the soft-decision read thresholds based on a genetic algorithm to obtain an optimal quantization interval. According to the invention, polar codes can be directly used for MLC flash channels without the arduous work of MLC flash channel modeling, so that the reliability of MLC flash is effectively improved.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 23, 2024
    Assignee: FUZHOU UNIVERSITY
    Inventors: Pingping Chen, Zhen Mei, Yi Fang, Xu Luo, Zhijian Lin, Feng Chen, Riqing Chen
  • Patent number: 11960434
    Abstract: A communication device includes: a communication unit that adds, to a set of data blocks including a serial signal group conforming to SPI transmitted from a master in synchronization with a clock, identification information for identifying the data blocks, and transmits the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or adds, to data blocks each including a part of the serial signal group, identification information for identifying each of the data blocks, and transmits the data blocks to the communication partner device in a plurality of frame periods; and a storage unit that sequentially stores a predetermined number of data blocks transmitted from the master and outputs a data block transmitted from the communication partner device in response to the predetermined number of data blocks from the master and stored, to transmit the data block to the master.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: April 16, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Toshihisa Hyakudai, Junya Yamada, Satoshi Ota
  • Patent number: 11960748
    Abstract: A method of operating a Solid State Drive (SSD), comprising identifying critical metadata corresponding to data previously written to the SSD. In response to a power loss event the method also includes storing the critical metadata in a non-volatile memory. Further, the method also involves writing a first table of contents corresponding to the stored critical metadata to the non-volatile memory and storing a pointer to the first table of contents. A Solid State Drive (SSD) including a memory controller, a non-volatile memory, and a power loss protection capacitor. The memory controller is configured to identify critical metadata corresponding to data previously written to the SSD. The memory controller is also configured to, in response to a power loss event, store the critical metadata in a non-volatile memory write a first table of contents corresponding to the stored critical metadata to the non-volatile memory, and store a pointer to the first table of contents.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: April 16, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Amit Jain
  • Patent number: 11947472
    Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 2, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Shreyas Shah, George Apostol, Jr., Nagarajan Subramaniyan, Jack Regula, Jeffrey S. Earl
  • Patent number: 11947466
    Abstract: A nonvolatile memory system is disclosed. The nonvolatile memory system includes a host device and a storage device connected to the host device through a physical cable including a power line and a data line. The storage device includes: a nonvolatile memory; a link controller configured to temporarily deactivate the data line while supplying power from the host device through the power line; and a memory controller including a user verification circuit configured to authenticate a user of the storage device and change a state of the memory controller according to a verification result, a relink trigger circuit configured to control the link controller based on the state change of the memory controller, and a data processing circuit configured to encrypt and decrypt data.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwasoo Lee, Mingon Shin, Seungjae Lee, Myeongjong Ju
  • Patent number: 11940933
    Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: March 26, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
  • Patent number: 11934336
    Abstract: Aspects of the disclosure provide an interface between a host and a multi-plane flash memory. For example, the interface can include a first storage unit, a second storage unit and a controller. The first storage unit can be configured to receive and store a first plane pipeline command issued from the host, and output the first plane pipeline command to a first plane of the flash memory. The second storage unit can be configured to receive and store a second plane pipeline command issued from the host, and output the second plane pipeline command to a second plane of the flash memory. The controller can be electrically connected to the first storage unit and the second storage unit, and configured to output the first and second plane pipeline commands to the first and second planes, respectively, when no read process is performed on the first plane and the second plane.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: March 19, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Xiaojiang Guo
  • Patent number: 11921650
    Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Rambus Inc.
    Inventor: Liji Gopalakrishnan
  • Patent number: 11907563
    Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yueh-Hung Chen, Chih-Kuo Kao, Ying Yu Tai, Jiangli Zhu
  • Patent number: 11892958
    Abstract: The present description concerns attribution, on a communication over an I2C bus, of a first address to a first device by a second device, wherein the second device sends the first address over the I2C bus and, if the second device receives no acknowledgment data, then the first device records the first address.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 6, 2024
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Fran├žois Tailliet