Abstract: A processing system has at least one internal processing unit and associated memory. The memory is accessible by at least two other independent processing units, and the memory of the at least one internal processing unit includes a data structure shared by the at least two other independent processing units that are allowed to perform direct memory writes into the shared data structure. A dedicated set of one or more bits in the shared data structure is allocated to each one of the at least two other independent processing units, each bit or each group of bits in the shared data structure indicates a unique combination of independent processing unit and application handler for handling an application in relation to the corresponding independent processing unit. Preparation and/or activation of the application handler indicated by the set bit or the set group of bits is initiated.

Abstract: Embodiments of the present disclosure disclose a method for transmitting terminal information and a related product. The method includes: receiving, by a first network element included in a network device, first information from a terminal.

Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

Abstract: Systems, apparatuses, methods, and computer-readable media are provided for device interface management. A device includes a device interface, a virtual machine (VM) includes a device driver, both to facilitate assignment of the device to the VM, access of the device by the VM, or removal of the device from being assigned to the VM. The VM is managed by a hypervisor of a computing platform coupled to the device by a computer bus. The device interface includes logic in support of a device management protocol to place the device interface in an unlocked state, a locked state to prevent changes to be made to the device interface, or an operational state to enable access to device registers of the device by the VM or direct memory access to memory address spaces of the VM, or an error state. Other embodiments may be described and/or claimed.

Abstract: A nonvolatile memory system is disclosed. The nonvolatile memory system includes a host device and a storage device connected to the host device through a physical cable including a power line and a data line. The storage device includes: a nonvolatile memory; a link controller configured to temporarily deactivate the data line while supplying power from the host device through the power line; and a memory controller including a user verification circuit configured to authenticate a user of the storage device and change a state of the memory controller according to a verification result, a relink trigger circuit configured to control the link controller based on the state change of the memory controller, and a data processing circuit configured to encrypt and decrypt data.

Abstract: This disclosure relates to a method for situation-dependent storage of data of a system, in which data of the system is detected, is amalgamated in at least one data block and is stored in a volatile memory, and in which, in response to the occurrence of at least one predefined trigger event in the at least one data block, amalgamated data are transferred from the volatile memory into a read-only memory, and in which a time window, in which the data for the at least one data block is captured, is selected automatically and dynamically according to the at least one trigger event.

Abstract: Examples may include a method of protecting memory and I/O transactions. The method includes allocating memory for an application, assigning a resource of a physical device to the application, assigning a process address space identifier to the assigned resource, creating a security enclave to protect the allocated memory of the application, and associating the security enclave with the process address space identifier to protect the allocated memory and the assigned resource.

Abstract: A storage device includes a memory and a memory controller which transmits a command to the memory. The memory includes at least one memory cell array, a memory temperature sensor which measures a temperature of the memory, and a control logic. The control logic outputs a busy signal in response to the command, receives the temperature of the memory from the memory temperature sensor in response to the command, and determines whether to perform a command operation according to the command on the memory cell array based on the received temperature of the memory.

Abstract: Systems and methods for peer storage devices to share host control data are described. Storage devices may include a host interface configured to connect to a host system and a control bus interface to connect to a control bus. Peer storage devices may establish peer communication through the control bus interface to share host control data, such as access parameters for host resources allocated to peer storage devices. A storage device may access host resources using access parameters allocated to that device, receive peer access parameters from a peer storage device, and access host resources allocated to the peer storage device using the peer access parameters. For example, a storage device may use a peer host memory buffer to store buffer data prior to releasing the host memory buffer allocated to it.

Abstract: Disclosed approaches eliminate involving a bus interface in polling by the host computer system and the peripheral component for events to coordinate direct memory access (DMA) transfers. The host polls main memory for DMA events communicated by the peripheral component, and the peripheral component polls local registers for DMA addresses to initiate DMA transfers. DMA transfers are initiated by the host storing main memory addresses in the local registers of the peripheral component, and DMA events generated by the peripheral component are stored in the main memory.

Abstract: A memory system includes a memory device suitable for storing data and a controller suitable for determining an operation state of the memory device and carrying out garbage collection to the memory device in response to the operation state. The controller can ignore a first command entered from a host while performing the garbage collection.

Abstract: A cache and memory coherent system includes multiple processing chips each hosting a different subset of a shared memory space and one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select one of the multiple processing chips. The system further includes a coherent mesh fabric that physically couples together each pair of the multiple processing chips, the coherent mesh fabric being configured to execute routing logic for updating the one or more routing tables responsive to identification of a first processing chip of the multiple processing chips hosting a defective hardware component, the update to the routing tables being effective to remove all access routes having endpoints corresponding to the first processing chip.

Abstract: Systems and methods for sampling a set of block IDs to facilitate estimating an amount of data stored in a data set of a storage system having one or more characteristics are provided. According to an example, metadata (e.g., block headers and block IDs) may be maintained regarding multiple data blocks of the data set. When one or more metrics relating to the data set are desired, an efficiency set, representing a subset of the block IDs of the data set, may be created to facilitate efficient calculation of the metrics by statistically sampling the block IDs of the data set. Finally, the metrics may be estimated based on the efficiency set by analyzing one or more of the metadata (e.g., block headers) and the data contained in the data blocks corresponding to the subset of the block IDs and extrapolating the metrics for the entirety of the data set.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

Abstract: There is provided a smart engine including a profile collector and a main processing module. The profile collector is configured to store a plurality of profiles, one or more suitable profiles being dynamically selected according to an instruction from a user or an automatic selector. The main processing module is connected to the profile collector and directly or indirectly connected to a sensor, and configured to perform a detailed analysis to determine detailed properties of features, objects, or scenes based on suitable sensor data from the sensor.

Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.

Abstract: A rack-mounted system includes a chassis, a switchless board disposed in the chassis, a midplane, and a plurality of device ports. The switchless board includes a baseboard management controller (BMC), a network repeater configured to transport network signals, and a PCIe switch configured to transport PCIe signals. Each of the plurality of device ports is configured to connect a storage device to the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable to operate in one of multiple storage protocol modes based on a type of the chassis. The network repeater of the switchless board is swappable with an Ethernet switch to provide a switching compatibility to the chassis using the same midplane. The storage device can operate in single-port and dual-port configurations.

Abstract: Disclosed is an evaluation system for evaluating a resource operation of an information system by a user. The evaluation system includes one or more arithmetic units, and one or more storage devices. The one or more storage devices are configured to store risk management information for managing an erroneous operation risk evaluation index relating to the resource operation of the information system. The one or more arithmetic units are configured to: receive operation information indicating a first resource operation designated by a first user, and evaluate an erroneous operation risk of the first resource operation based on the first resource operation and the risk management information.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.

Abstract: In some examples, a system assigns workload fingerprints to each respective storage volume of a plurality of storage volumes, the workload fingerprints assigned to the respective storage volume across a plurality of points. Based on the workload fingerprints assigned to respective storage volumes of the plurality of storage volumes, the system groups the storage volumes into clusters of storage volumes. The system manages an individual cluster of the clusters of storage volumes according to an attribute associated with the individual cluster.