Abstract: A user station for a bus system and a method for transmitting a message at different bit rates in a bus system. The user station includes a communication control unit for creating a message for a further user station of the bus system. The communication control unit provides, in the message, a first phase, which is to be transmitted at a first bit rate, and to provide a second phase, which is to be transmitted at a second bit rate, which is faster than the first bit rate. The communication control unit is designed to provide in the message a first predetermined bit pattern for a bit rate switching between the first and second bit rate and to provide a second predetermined bit pattern for a bit rate switching between the second and first bit rate. The second predetermined pattern differs from all other bit patterns in a valid message.

Abstract: An example method may include allocating, on a host computer system, a memory page in a memory of an input/output (I/O) device, mapping the memory page into a memory space of a virtual machine associated with a first virtual processor, creating a first entry in an interrupt mapping table in the memory of the I/O device, where the first entry includes a memory address that is associated with a second virtual processor identifier and further includes an interrupt vector identifier; and creating a second entry in an interrupt injection table of an interrupt injection unit of the host computer system, where the second entry is associated with a memory address that corresponds to a second virtual processor, the second entry includes the interrupt vector identifier, and the second entry is further associated with the second virtual processor identifier.

Abstract: A data processing method includes sending, by a network interface card of a first device, a request packet to a second device. The request packet is used to request to read data in a destination storage area of the second device. The network interface card receives a response packet that is sent by the second device in response to the request packet. The response packet includes the data. The network interface card initiates, based on the response packet, direct memory access to a storage address to write the data into a memory area to which the storage address points. The first data does not need to be cached in a memory of the network interface card. Bandwidth resource usage and storage space usage of the memory of the network interface card can be reduced.

Abstract: An apparatus comprises a first processing device, the first processing device comprising a physical hardware controller configured for coupling with a second processing device. The first processing device is configured to identify one or more remote storage service instances attached to the second processing device, and to initiate storage emulation modules for the remote storage service instances attached to the second processing device, the storage emulation modules emulating one or more physical storage devices configured for attachment to the second processing device.

Abstract: The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.

Abstract: A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.

Abstract: An integrated circuit for allowing a band of an external memory to be effectively used in processing a layer algorithm is disclosed. One aspect of the present disclosure relates to an integrated circuit including a first arithmetic part including a first arithmetic unit and a first memory, wherein the first arithmetic unit performs an operation and the first memory stores data for use in the first arithmetic unit and a first data transfer control unit that controls transfer of data between the first memory and a second memory of a second arithmetic part including a second arithmetic unit, wherein the second arithmetic part communicates with an external memory via the first arithmetic part.

Abstract: Read latency for a read operation to a host implementing a PRP/SGL buffer is reduced by generating an address table representing the linked-list structure defining the PRP/SGL buffer. The address table may be generated concurrently with reading of data referenced by the read command from a NAND storage device. A block table for tracking status of LBAs referenced by IO commands may include a reference to the address table which is used to transfer LBAs to host memory as soon as the address table is complete and a block of data referenced by an LBA has been read from the NAND storage device.

Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: Methods, systems, and apparatuses related to configured dual register clock driver (RCD) devices on a single memory subsystem using different configuration information are described. In some examples, configuration of the two RCD devices with different configuration information may include use of a serial data bus to receive and store first RCD configuration data, which is provided to both of the RCD devices to configure one or more parameters of each respective RCD device. One of the RCD devices may receive second configuration data via a command and address bus to independently update the one or more configuration parameters of one of the two RCD devices.

Abstract: Systems and methods are disclosed for training a previously trained neural network with incremental dataset. Original train data is provided to a neural network and the neural network is trained based on the plurality of classes in the sets of training data and/or testing data. The connected representation and the weights of the neural network is the model of the neural network. The trained model is to be updated for an incremental train data. The embodiments provide a process by which the trained model is updated for the incremental train data. This process creates a ground truth for the original training data and trains on the combined set of original train data and the incremental train data. The incremental training is tested on a test data to conclude the training and to generate the incremental trained model, minimizing the knowledge learned with the original data. Thus, the results remain consistent with the original model trained by the original dataset except the incremental train data.

Abstract: The disclosure provides a read/write control method and device for a DDR (Double Data Rate) dynamic random access memory, and a system. The device comprises a read control signal generating unit and a read memory controller, and the read control signal generating unit is in signal connection with the read memory controller; the read control signal generating unit is configured for determining a minimum frame period from multiple received signal sources, generating a read control signal based on the minimum frame period, and providing the read control signal to the read memory controller; and the read memory controller is configured for controlling the reading of video frames from the DDR dynamic random access memory according to the read control signal.

Abstract: Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

Abstract: An apparatus that operates in a first mode of operation to enable performance of a first predetermined task to transfer data via a transmitter device to a receiver device across a first communication channel using a first artificial neural network, wherein the first artificial neural network is partitioned to the transmitter device and the receiver device, and operate in a second mode of operation to enable performance of a second predetermined task to transfer data via the transmitter device to the receiver device across a second communication channel using a second artificial neural network, wherein the second artificial neural network is partitioned to the transmitter device and the receiver device, and determine to operate the apparatus in the first mode or the second mode.

Abstract: A processing system has at least one internal processing unit and associated memory. The memory is accessible by at least two other independent processing units, and the memory of the at least one internal processing unit includes a data structure shared by the at least two other independent processing units that are allowed to perform direct memory writes into the shared data structure. A dedicated set of one or more bits in the shared data structure is allocated to each one of the at least two other independent processing units, each bit or each group of bits in the shared data structure indicates a unique combination of independent processing unit and application handler for handling an application in relation to the corresponding independent processing unit. Preparation and/or activation of the application handler indicated by the set bit or the set group of bits is initiated.

Abstract: Embodiments of the present disclosure disclose a method for transmitting terminal information and a related product. The method includes: receiving, by a first network element included in a network device, first information from a terminal.

Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

Abstract: Systems, apparatuses, methods, and computer-readable media are provided for device interface management. A device includes a device interface, a virtual machine (VM) includes a device driver, both to facilitate assignment of the device to the VM, access of the device by the VM, or removal of the device from being assigned to the VM. The VM is managed by a hypervisor of a computing platform coupled to the device by a computer bus. The device interface includes logic in support of a device management protocol to place the device interface in an unlocked state, a locked state to prevent changes to be made to the device interface, or an operational state to enable access to device registers of the device by the VM or direct memory access to memory address spaces of the VM, or an error state. Other embodiments may be described and/or claimed.