Patents Examined by Eric Wendler
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Patent number: 7940560Abstract: A memory device is provided which includes a write bit line, a read bit line, and at least one memory cell. The memory cell includes a write access transistor, a read access transistor coupled to the read bit line and to the first write access transistor, and a gated-lateral thyristor (GLT) device coupled to the first write access transistor. Among its many features, the memory cell prevents read disturbances during read operations by decoupling the read and write bit lines.Type: GrantFiled: May 29, 2008Date of Patent: May 10, 2011Assignee: Advanced Micro Devices, Inc.Inventor: Hyun-Jin Cho
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Patent number: 7826272Abstract: The present invention solves a problem of the degradation of the long-term reliability of a conventional semiconductor memory device due to early deterioration of a FET included in a reference cell therein. DRAM 1 has word lines 101 to 10n, word lines 22 and 24, memory cells 301 to 30n and a reference cell 40. Gates of FETs 32 in the memory cells 301 to 30n are connected to the word lines 101 to 10n respectively. Gates of a FET 42 and a FET 44 in the reference cell 40 are connected to the word line 22 for readout and the word line 24 for writing respectively. Here, potentials applied to the word lines 22 and 24 are lower than those applied to the word lines 101 to 10n.Type: GrantFiled: August 9, 2007Date of Patent: November 2, 2010Assignee: NEC Electronics CorporationInventor: Takashi Sakoh
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Patent number: 7782684Abstract: A semiconductor memory device is capable of controlling a tRCD (RAS to CAS Delay) time regardless of an address input timing during a test operation of the semiconductor memory device. The semiconductor memory device includes a column address strobe pulse generator for generating a column address strobe pulse in response to a column command signal and a row address strobe pulse generator for receiving an active command signal or the column command signal to produce a row address strobe pulse in response to a test mode signal.Type: GrantFiled: December 5, 2007Date of Patent: August 24, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Jae-Hoon Cha, Byoung-Jin Choi
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Patent number: 7778088Abstract: A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase pulse count corresponding to a preliminary erase operation during which a relatively small portion of a sector is erased. The adjustment of the erase bias voltage in this manner enables the rest of the sector to be erased using erase bias voltages that are better suited to the current erase characteristics of the sector.Type: GrantFiled: December 19, 2006Date of Patent: August 17, 2010Assignee: Spansion LLCInventors: Kuo-Tung Chang, Wei Zheng
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Patent number: 7773447Abstract: A memory circuit of the invention comprises N look-up tables for implementing a desired logic function of L inputs/M outputs by partitioning a memory cell array including a plurality of memory cells into portions each corresponding to at least a predetermined number of input/output paths; a decode circuit for selecting one of the N look-up tables by decoding a look-up table select signal and for selecting M memory cells to be accessed included in the selected look-up table by decoding an L-bit logic input signal of the logic function; and a select connect circuit for selectively connecting the input/output paths of the M memory cells to be accessed with an input/output bus for transmitting an M-bit logic output signal of the logic function in response to a decoded result of the decode circuit.Type: GrantFiled: October 29, 2007Date of Patent: August 10, 2010Assignee: Elpida Memory, Inc.Inventor: Kazuhiko Kajigaya
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Patent number: 7768813Abstract: In one embodiment, a DRAM is provided that includes: a word line intersecting with a pair of bit lines, the DRAM including a memory cell at each intersection, each memory cell including an access transistor adapted to couple a storage cell to the corresponding bit line if its gate voltage is raised; and a word line compensation circuit adapted to compensate for a capacitively-coupled voltage increase on the corresponding bit line if the access transistor's gate voltage is raised.Type: GrantFiled: August 27, 2007Date of Patent: August 3, 2010Assignee: Novelics, LLC.Inventors: Esin Terzioglu, Melinda L. Miller
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Patent number: 7768835Abstract: A memory device having memory cells fabricated in a substrate well is described. The memory device includes control circuitry to perform an erase operation on the memory cells and a voltage bias circuit to bias the substrate well to a positive voltage level during an erase verification operation of memory cells. The voltage bias circuit controls a discharge level of the substrate well following the erase operation to prevent the substrate well from fully discharging lower than the positive voltage level.Type: GrantFiled: August 9, 2006Date of Patent: August 3, 2010Assignee: Micron Technology, Inc.Inventor: Akira Goda
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Patent number: 7764536Abstract: A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disables at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.Type: GrantFiled: August 7, 2007Date of Patent: July 27, 2010Assignees: Grandis, Inc., Renesas Technology Corp.Inventors: Xiao Luo, David Chang-Cheng Yu
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Patent number: 7760567Abstract: A first precharge circuit couples a bit line pair to a precharge voltage line in a standby period, and separates at least an access side of the bit line pair from the precharge voltage line in accordance with operation start of a word line driving circuit. A sense amplifier amplifies a voltage difference of a node pair after the operation start of the word line driving circuit. A switch circuit is provided between the bit line pair and the node pair. The switch circuit has coupled the access side of the bit line pair to an access side of the node pair at an instant of the operation start of the word line driving circuit, and has separated a non-access side of the bit line pair from a non-access side of the node pair at an instant of operation start of the sense amplifier.Type: GrantFiled: September 19, 2008Date of Patent: July 20, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Hiroyuki Kobayashi
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Patent number: 7755958Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.Type: GrantFiled: July 20, 2007Date of Patent: July 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-yong Byun, Hi-choon Lee
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Patent number: 7755964Abstract: A memory device with configurable delay tracking is described. The memory device includes M normal word line drivers, a dummy word line driver a memory array, N sense amplifiers, and a timing control circuit. The memory array includes M rows and N columns of memory cells and a column of dummy cells. The word line drivers drive word lines for the rows of memory cells. The dummy word line driver drives a dummy word line for at least one dummy cell in the column of dummy cells. The timing control circuit generates enable signals having configurable delay, which may be obtained with an acceleration circuit that provides variable drive for a dummy bit line coupled to the column of memory cells. The sense amplifiers detect bit lines for the columns of memory cells based on the enable signals.Type: GrantFiled: October 25, 2006Date of Patent: July 13, 2010Inventors: Seong-Ook Jung, Sei Seung Yoon, Yi Han
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Patent number: 7746717Abstract: A static random access memory (SRAM) can include an array of memory cells, wherein each memory cell is coupled to one of a plurality of sense amplifiers through a bitline. The SRAM also can include replica bitline circuitry including a replica bitline coupled to a replica bitline amplifier. The replica bitline amplifier can provide a strobe signal to the plurality of sense amplifiers, wherein the replica bitline amplifier includes a feedback path. An SRAM also may include a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array can be turned off responsive to the signal.Type: GrantFiled: September 7, 2007Date of Patent: June 29, 2010Assignee: Xilinx, Inc.Inventors: Tao Peng, Hsiao Hui Chen
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Patent number: 7746690Abstract: A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.Type: GrantFiled: March 28, 2007Date of Patent: June 29, 2010Assignee: Sanyo Electric Co., Ltd.Inventor: Kouichi Yamada
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Patent number: 7742346Abstract: A voltage booster and a memory structure using the same are provided. When a data storage unit in the memory structure is in normal operation, all voltage pumps in the voltage booster are turned on for boosting a supply voltage. However, when the data storage unit is in standby state, in the voltage booster, some voltage pumps are turned on while other voltage pumps are turned off, for boosting the supply voltage. Accordingly, the standby current and power consumption are reduced and the pump efficiency is improved.Type: GrantFiled: August 22, 2007Date of Patent: June 22, 2010Assignee: Nanya Technology CorporationInventor: Chih-Jen Chen
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Patent number: 7742356Abstract: A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.Type: GrantFiled: December 4, 2007Date of Patent: June 22, 2010Assignee: Elpida Memory, Inc.Inventors: Chiaki Dono, Yasuji Koshikawa
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Patent number: 7738307Abstract: A semiconductor device is capable of minimizing data skew among respective data which are transmitted to a receiver through respective data lines. The semiconductor device includes a synchronization unit connected to at least one portion of the respective data lines, for synchronizing time that the plurality of data transferred through the respective data lines take to arrive at the receiver.Type: GrantFiled: September 29, 2006Date of Patent: June 15, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Seong-Hwi Song
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Patent number: 7733690Abstract: A semiconductor integrated circuit comprising a data holding circuit sets the data holding circuit to a desired data state by first setting the power-supply voltage of the data holding circuit to be less than a specified voltage, and then setting the power-supply voltage of the data holding circuit to the specified voltage or greater, regardless of the data state that is stored beforehand in the data holding circuit.Type: GrantFiled: July 20, 2007Date of Patent: June 8, 2010Assignee: Panasonic CorporationInventor: Tomoyuki Kumamaru
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Patent number: 7724575Abstract: In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.Type: GrantFiled: February 21, 2008Date of Patent: May 25, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Soo Lee, Young-Ho Lim, Hyun-Chul Cho, Dong-Hyuk Chae
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Patent number: 7719907Abstract: A semiconductor memory device is capable of performing a normal operation, while detecting an internal voltage without a special bonding method during a test mode. The semiconductor memory device comprises a switching unit and an internal reference voltage generating unit. The switching unit transfers one of an internal and an external reference voltages according to whether a test mode is being performed, wherein the external reference voltage is input from outside of the semiconductor memory device. The internal reference voltage generating unit generates the internal reference voltage having the same level of the external reference voltage to thereby supply the internal reference inside the semiconductor memory device during the test mode.Type: GrantFiled: March 14, 2007Date of Patent: May 18, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Kee-Teok Park
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Patent number: 7719900Abstract: A semiconductor storage device which includes a memory array including a plurality of memory cells for storing data by using a difference in a threshold voltage and at least one reference cell for storing data indicative of a state of a corresponding memory cell by using a difference in a threshold voltage, a control circuit for determining a read voltage based on data stored by a reference cell corresponding to a memory cell adjacent to a memory cell to be read, a read unit for executing reading from a memory cell to be read by using a determined read voltage, and a write unit for executing writing, when executing writing to a memory cell to be written to bring the memory cell into a written state, data indicating that the memory cell is in the written state to a reference cell corresponding to the memory cell.Type: GrantFiled: June 27, 2006Date of Patent: May 18, 2010Assignee: Renesas Technology Corp.Inventors: Shota Okayama, Ken Matsubara