Abstract: A synchronous semiconductor memory device including a data alignment reference pulse generating unit configured to generate a data alignment reference pulse in response to a data strobe signal (DQS), an alignment hold signal generating unit configured to generate an alignment hold signal, which is activated during a period corresponding to a postamble of the data strobe signal, in response to the data alignment reference pulse and a data input clock, and a data alignment unit configured to align input data in response to the data alignment reference pulse and the alignment hold signal.

Abstract: A power supply circuit for a sense amplifier of a semiconductor memory device includes a first reference voltage supplier configured to output a first reference voltage when a control signal is activated upon a write operation, a second reference voltage supplier configured to output a second reference voltage when the control signal is deactivated upon a read operation, and a core voltage source configured to receive the first reference voltage or the second reference voltage and generate a core voltage.

Abstract: The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the storage device of the invention, an ID comparator determines whether or not identification data transmitted from a host computer coincides with identification data stored in a memory array. In the case of coincidence, the ID comparator sends an access enable signal EN to an operation code decoder. The operation code decoder analyzes a write/read command, switches over a direction of data transfer with regard to the memory array based on a result of the analysis, and requires an I/O controller to change a high impedance setting of a signal line connecting with a data terminal DT. This series of processing allows access to an address in the memory array specified by a count on an address counter.

Abstract: To fully evaluate a real signal line and a real memory cell adjacent to a dummy signal line and utilize dummy signal line as real signal line, a semiconductor memory includes at least one real signal line connected to real memory cells driven by a real driver and at least one dummy signal line outside the real signal line connected to dummy memory cells, driven by a dummy driver. Real driver and dummy driver drive the real signal line and the dummy signal line synchronous with a common timing signal generated by an operation control circuit. Consequently, a stress evaluation is also performable, e.g., on a real signal line outside of a memory cell array under the same condition of a real signal line on the inner side. Dummy signal line is driven using common timing signal and evaluated, thus being usable as a redundancy signal line to relieve failure.

Abstract: Methods, apparatus, and systems in accordance with this invention include memories that include a data array and a configuration array adapted to store configuration information for configuring the data array. The data array and the configuration array include a plurality of wordlines and a plurality of bitlines. The plurality of wordlines in the data array extend in the same direction as the plurality of wordlines in the configuration array. Likewise, the plurality of bitlines in the data array extend in the same direction as the plurality of bitlines in the configuration array. The configuration array may include a wordline driver layout, a bitline driver layout, relative positions of zia contact regions, a diode sensing orientation, a sense amplifier layout, a voltage regulator layout, and a layout of conductors proximate to the array that are each substantially similar to corresponding elements of the data array. Numerous other aspects are disclosed.

Abstract: An electrical fuse circuit including: a capacitor composing an electrical fuse; a write circuit breaking an insulating film of the capacitor by applying voltage to between both terminals of the capacitor in accordance with a write signal; and a precharge circuit precharging with respect to the terminal of the capacitor, is provided.

Abstract: A redundant cross point switching is achieved by mapping a redundant column/row of point cells and enabling at least one of the switching devices which is associated with each column/row to define an alternate path around the defective point cell which replicates the function of the switching location of the defective point cell.

Abstract: High speed SRAM is realized such that a first dynamic circuit serves as a local sense amp for reading a memory cell through a lightly loaded local bit line, a second dynamic circuit serves as a segment sense amp for reading the local sense amp, and a tri-state inverter serves as an inverting amplifier of a global sense amp for reading the segment sense amp. When reading, a voltage difference in the local bit line is converted to a time difference for differentiating low data and high data by the sense amps for realizing fast access with dynamic operation. Furthermore, a buffered data path is used for achieving fast access and amplify transistor of the sense amps is composed of relatively long channel transistor for reducing turn-off current. Additionally, alternative circuits and memory cell structures for implementing the SRAM are described.

Abstract: A memory system and method are described. For example, a memory cell includes a capacitance and an access circuit in association with the capacitance and having an access circuit terminal. The memory cell further includes a voltage control unit to adjust a potential at the access circuit terminal in a retention state such that a retention time of the memory cell is increased. A method of operating a memory cell includes, for example, adjusting a potential at an access circuit terminal of the memory cell to increase a retention time.

Abstract: A tree-structure memory device. A tree-structure memory device comprises a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction. A plurality of layers having a plurality of memory cells is arranged in a first array. At least one tree structure corresponds to a plurality of layers and a bit line, and has a trunk portion and at least one branch portion that corresponds to one of the layers. A word-line group includes at least one word line crossing with the branch portion of the tree structure at a first intersection region. A memory cell of the first array is located at the first intersection region in a layer of the layers. The first array of memory cells includes at least one memory cell comprising a phase-change-material layer disposed between the word line and the branch portion of the tree structure at the first intersection region without an intervening current-steering element.

Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Abstract: A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.

Abstract: The present invention relates to a column decoder for low power consumption in a semiconductor memory apparatus. The semiconductor device according to the present invention includes a column select signal decoder, which has a driving voltage input node and uses a driving voltage, for producing a plurality of column select signals by decoding a column select control signal; and a driving voltage supply controller for controlling a supply of the driving voltage to the driving voltage input node.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays that may be configured for true dual port operation or simple dual port operation. The memory arrays include memory cells arranged in rows and columns and associated row address lines and data lines. Sense amplifiers and write drivers are used for reading and writing data. Precharge drivers are used to precharge the data lines prior to read operations. Configurable multiplexer circuitry in the array has read paths through which data is provided to the sense amplifiers from the memory cells. The multiplexer circuitry has write paths through which data from the write drivers is written into the memory cells. The read paths and the write paths contain no more than a single pass gate each. Each precharge driver may be connected to a respective one of the data lines with no intervening pass gates.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A memory device may include a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. Moreover, the string selection transistor may be coupled between the string and a bitline, and the ground selection transistor may be coupled between the string and a common source line. During programming, one of the plurality of memory cell transistors in the string may be selected for a program operation so that other memory cell transistors in the string are unselected, and a plurality of negative voltage pulses may be applied to a channel region of the selected memory cell transistor. While applying the plurality of negative voltage pulses to the channel region, a positive pass voltage may be applied to control gate electrodes of the unselected memory cell transistors, and a positive program voltage may be applied to a control gate electrode of the selected memory cell. Related methods and devices are discussed.

Abstract: In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed MRS decoded signal, switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles, performing a MRS command to a mode register of the DRAM device, and switching back to the first command timing frequency.

Abstract: A memory device and method of operation is provided, the memory device having a plurality of memory cells arranged in at least one column, with each column having at least one bit line and a supply voltage line associated therewith. A capacitance exists between the supply voltage line and associated at least one bit line for each column. Control circuitry is used to control, for each column, connection of a voltage source to the associated supply voltage line. For a predetermined period during a memory access operation, the control circuitry disconnects the supply voltage line for at least the selected column from the voltage source, such that a voltage level on that supply voltage line changes in response to any change in voltage on the associated at least one bit line. This basic mechanism can be used to provide a variety of assist mechanisms, such as a write assist mechanism, a bit flip assist mechanism and a read assist mechanism.

Abstract: A memory device and method of operation are provided. The memory device comprises a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column. A supply voltage line is associated with each column, the supply voltage line being connectable to a first voltage source to provide a supply voltage at a first voltage level to the associated column. Threshold circuitry is connected to a second voltage source having a second voltage level, the threshold circuitry having a threshold voltage. Control circuitry is used during the write operation to disconnect the supply voltage line for the selected column from the first voltage source, and to connect the threshold circuitry to the supply voltage line for the selected column.

Abstract: A memory device, and methods relating thereto, having memory cells in which a single an access transistor controls the grounding of at least two storage resistive memory elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently. The storage elements are disposed in respective layers. Each storage element is coupled to first and second conductors having for reading the memory that have respective, parallel, longitudinal axes. The longitudinal axes are oriented substantially parallel to one another, at least in proximity to a particular storage element.