Abstract: The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.
Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.
Abstract: The present invention provides QLED devices, hole transport materials and producing methods thereof, and display devices. A hole transport material includes a polymer, wherein the polymer is a single nanoparticle including at least a first metal compound and a second metal compound, the first metal compound and the second metal compound are linked via a covalent bond or a Van der Waals force, and valence band energy levels of the first metal compound and the second metal compound are different.
Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.
Abstract: An inductor device includes a first wire, a second wire, a third wire, a fourth wire and an 8-shaped inductor structure. The first wire is disposed in a first area. The second wire is disposed in a second area. The third wire is disposed in the first area and at least partially overlapped with the first wire in a vertical direction. The third wire includes at least two third sub-wires, and the at least two third sub-wires are arranged with an interval between each other. The fourth wire is at least partially overlapped with the second wire in the vertical direction. The fourth wire includes at least two fourth sub-wires, and the at least two fourth sub-wires are arranged with an interval between each other. The eight-shaped inductor structure is disposed on an outer side of the third wire and the fourth wire.
Abstract: A display device including a display panel and a support layer is provided. The display panel has a light-transmitting area and a bonding area connected to the light-transmitting area. The support layer includes a first support layer and a second support layer, where the first support layer has a first portion corresponding to the light-transmitting area, the second support layer has a second portion corresponding to the bonding area, and an optical phase retardation coefficient of the first portion is less than an optical phase retardation coefficient of the second portion.
Type:
Grant
Filed:
February 26, 2021
Date of Patent:
January 14, 2025
Assignee:
Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
Inventors:
Yunti Zhang, Dong Zhan, Hanning Yang, Xin Liu
Abstract: A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising an elastic material and a superconductor film, releasing a portion of the elastic material by selective removal of the release film so that portion lifts out of the substrate plane to form elastic springs. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising at least an elastic material, releasing a portion of the elastic material so that portion lifts out of a plane of the substrate to form elastic springs, and coating the elastic springs with a superconductor film.
Abstract: A color conversion composition that converts incident light into light having a longer wavelength than the incident light is described, the color conversion composition including the following components (A) and (B): component (A): an organic light-emitting material; and component (B): a resin whose molecular structure has a fluorene skeleton.
Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
Abstract: Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.
Type:
Grant
Filed:
September 20, 2017
Date of Patent:
November 26, 2024
Assignee:
Intel Corporation
Inventors:
Kevin L. Lin, Nicholas James Harold McKubre, Han Wui Then
Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.
Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.
Abstract: Provided are a dipolar molecule-stabalized perovskite material and an optoelectronic device. The invention aims to provide the perovskite material with the stable dipolar molecules and the optoelectronic device, which can indirectly enhance an interaction between metal cations and halogen anions, reduce a defect state density in the perovskite material, and inhibit ion migration in the perovskite material by utilizing dipolar groups in a dipolar molecule stabilizer. A component of the perovskite material with the stable dipolar molecules is D: A? 2An-1BnX3n+1 or D: ABX3, wherein A? is an organic amine cation, A is a monovalent cation, B is a metal cation, X is a monovalent anion, and D is the dipolar molecule stabilizer. A thermal stability, a phase stability and a photoluminescence stability of the material are remarkably enhanced, and working stabilities and efficiencies of the perovskite material and the optoelectronic device are remarkably improved.
Abstract: A semiconductor device includes first and second active regions parallel to each other and respectively extending in a first direction, an isolation layer between the first and second active regions, a first line structure and a second line structure overlapping the first and second active regions and the isolation layer, parallel to each other, and extending in a second direction, a first source/drain region on the first active region, and a second source/drain region on the second active region. The first line structure includes a first gate structure, a second gate structure, and a first insulating separation pattern between the first and second gate structures. The second line structure includes a third gate structure, a fourth gate structure, and a second insulating separation pattern between the third and fourth gate structures. The first and second insulating separation patterns are spaced apart from each other.
Abstract: Provided are a light-emitting device including a condensed cyclic compound represented by Formula 1, and an electronic apparatus including the light-emitting device. The light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an interlayer between the first electrode and the second electrode and comprising an emission layer, wherein the light-emitting device further comprises a second capping layer outside the second electrode, the second capping layer having a refractive index of equal to or greater than 1.6, and the emission layer comprises at least one condensed cyclic compound represented by Formula 1.
Type:
Grant
Filed:
April 5, 2021
Date of Patent:
October 22, 2024
Assignee:
Samsung Display Co., Ltd.
Inventors:
Munki Sim, Junha Park, Hankyu Pak, Jangyeol Baek, Chanseok Oh, Seokhwan Hwang, Taeil Kim, Sunyoung Pak, Hyoyoung Lee, Minjung Jung
Abstract: Described herein are transition metal complexes containing nickel(II), as the central metal atom, and tridentate and tetradentate ligands. The transition metal complexes also include an ancillary ligand with strong ?-donating properties. The ancillary ligand enhances the luminescence by increasing the chances of populating the emissive state. The transition metal complexes are emissive at room temperature and/or low temperature in various media, rendering them useful as light-emitting materials for OLEDs.
Abstract: A chip-transferring module, and a device and a method for transferring and bonding chips are provided. The chip-transferring module includes a mounting main body, a light-transmitting member, a first gas guiding structure and a second gas guiding structure. The mounting main body has a first accommodating space and a second accommodating space. The light-transmitting member is disposed in the first accommodating space. The first gas guiding structure is disposed in the mounting main body and has a plurality of suction openings exposed out of the mounting main body. The second gas guiding structure is disposed in the mounting main body and has at least one intake opening communicating with the second accommodating space.
Type:
Grant
Filed:
November 30, 2021
Date of Patent:
October 1, 2024
Assignee:
Micraft System Plus Co., Ltd.
Inventors:
Chien-Shou Liao, Shao-Wei Huang, Ching-Ju Lin
Abstract: A display device includes a pixel disposed in a display area. The pixel includes a first electrode and a second electrode spaced apart from each other; at least one intermediate electrode disposed between the first electrode and the second electrode; a plurality of light emitting elements electrically connected between a pair of adjacent electrodes of a plurality of electrodes including the first electrode, the second electrode, and the at least one intermediate electrode; and a plurality of repair patterns overlapping and disposed between a pair of adjacent electrodes of the plurality of electrodes.
Abstract: The present technology relates to a solid-state imaging element and electronic equipment that allow an increase in the signal charge amount Qs that each pixel can accumulate. A solid-state imaging element according to the first aspect of the present technology includes: a photoelectric conversion section formed in each pixel; and an inter-pixel separation section separating the photoelectric conversion section of each pixel, in which the inter-pixel separation section includes a protruding section having a shape protruding toward the photoelectric conversion section. The present technology can be applied to a back-illuminated CMOS image sensor, for example.
Type:
Grant
Filed:
May 31, 2023
Date of Patent:
September 24, 2024
Assignee:
Sony Semiconductor Solutions Corporation
Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.