Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

Abstract: Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate, and extend in a second direction, and have different lengths on the second region, channel structures that penetrate the gate electrodes, extend in the first direction, and respectively include a channel layer on the first region, support structures that penetrate the gate electrodes and extend in the first direction on the second region, and a separation region that penetrates the gate electrodes and extend in the second direction. The substrate has a recess region that overlaps the separation region in the first direction and extends downward from an upper surface in the second region, adjacent to the first region. The separation region has a protrusion that protrudes downward to correspond to the recess region.

Abstract: An electronic device may have image transport layer material such as coherent fiber bundle material or Anderson localization material. The image transport layer material may overlap optical components. Optical sensor components can emit and/or detect light passing through the image transport layer material. Optical components such as light-emitting diodes may emit light through image transport layers. An image from a display may pass through an image transport layer. Infrared light-emitting diodes, infrared photodetectors, and/or other optical sensor components may be used to form a two-dimensional optical touch sensor that is configured to gather touch input from an external object such as a finger of a user. The optical touch sensor may operate through an image transport layer.

Abstract: A microelectromechanical system (MEMS) device and method of fabrication are provided. The MEMS devices includes a silicon substrate. The silicon substrate includes a top surface. An interconnect is machined from the silicon substrate. The interconnect includes at a spring body that has least two spring arms. Each spring arm includes a first end distal from a center of the interconnect, a second end proximate the center of the interconnect, and a single turn of a constant curvature. Each spring arm is configured to move rotationally in a plane parallel to the top surface of the silicon substrate.

Abstract: This chip mounting system simultaneously images an alignment mark disposed on a substrate (WT) and an alignment mark disposed on a chip (CP), with the alignment marks disposed on the substrate (WT) and the chip (CP) being separated by a first distance at which the alignment marks fall within a depth-of-field range of imaging devices. The chip mounting system calculates a relative positional deviation amount between the substrate (WT) and the chip (CP) from the imaged images of the alignment marks imaged by the imaging devices and, based on the calculated positional deviation amount, relatively moves the chip (CP) with respect to the substrate (WT) in a direction in which the positional deviation amount therebetween decreases.

Abstract: A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.

Abstract: Systems and methods for performing non-destructive sensing of a cell or tissue, in vivo or in culture, are provided. The disclosed systems and methods include fabricating and powering one or more implantable integrated circuit (IC) chips that include a network of Photovoltaic (PV) cells for energy harvesting from an optical energy source, an optical modulator integrating Quantum Dot capacitors (QD-caps) for optical data transfer using fluorescence modulation, and sensing circuitry. The IC chip disclosed herein can measure a thickness of around 10 ?m, allowing injection into small cells and diffusion through tissue, it is powered and imaged under a microscope and communicates using fluorescence modulation imaged under a microscope.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: Provided are spiro-bisilepine compounds. Also provided are formulations comprising these spiro-bisilepine compounds. Further provided are OLEDs and related consumer products that utilize these spiro-bisilepine compounds.

Abstract: [Problem] To provide a method for manufacturing an element which does not lead to the occurrence of a short due to etching, and which suppresses the deterioration of a photoelectric conversion layer.

Abstract: The purpose of the present invention is to suppress a change in characteristics of a TFT using an oxide semiconductor film caused by that oxygen in the oxide semiconductor film is extracted by metal electrode. The main structure of the present invention is as follows. A semiconductor device having a TFT, in which a gate insulating film is formed on a gate electrode, and an oxide semiconductor film is formed on the gate insulating film; the oxide semiconductor film including a channel region, a drain region, and a source region; in which a metal nitride film is formed on a top surface of the gate electrode in an opposing portion to the channel region in a plan view; and the metal nitride film is not formed at a part of the top surface of the gate electrode.

Abstract: A coil component includes a support substrate having one surface including at least one groove portion; a coil portion disposed to contact the one surface of the support substrate; and a body embedding the support substrate and the coil portion, wherein the coil portion has an anchor portion disposed in the at least one groove portion, and a pattern portion disposed on the anchor portion and spaced apart from the one surface of the support substrate. A line width of the anchor portion is narrower than a line width of the pattern portion.

Abstract: The present invention provides QLED devices, hole transport materials and producing methods thereof, and display devices. A hole transport material includes a polymer, wherein the polymer is a single nanoparticle including at least a first metal compound and a second metal compound, the first metal compound and the second metal compound are linked via a covalent bond or a Van der Waals force, and valence band energy levels of the first metal compound and the second metal compound are different.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

Abstract: An inductor device includes a first wire, a second wire, a third wire, a fourth wire and an 8-shaped inductor structure. The first wire is disposed in a first area. The second wire is disposed in a second area. The third wire is disposed in the first area and at least partially overlapped with the first wire in a vertical direction. The third wire includes at least two third sub-wires, and the at least two third sub-wires are arranged with an interval between each other. The fourth wire is at least partially overlapped with the second wire in the vertical direction. The fourth wire includes at least two fourth sub-wires, and the at least two fourth sub-wires are arranged with an interval between each other. The eight-shaped inductor structure is disposed on an outer side of the third wire and the fourth wire.

Abstract: A display device including a display panel and a support layer is provided. The display panel has a light-transmitting area and a bonding area connected to the light-transmitting area. The support layer includes a first support layer and a second support layer, where the first support layer has a first portion corresponding to the light-transmitting area, the second support layer has a second portion corresponding to the bonding area, and an optical phase retardation coefficient of the first portion is less than an optical phase retardation coefficient of the second portion.

Abstract: A color conversion composition that converts incident light into light having a longer wavelength than the incident light is described, the color conversion composition including the following components (A) and (B): component (A): an organic light-emitting material; and component (B): a resin whose molecular structure has a fluorene skeleton.