Patents Examined by Ermias T Woldegeorgis
  • Patent number: 10658502
    Abstract: III-N transistor including a vertically-oriented lightly-doped III-N drift region between an overlying III-N 2DEG channel and an underlying heavily-doped III-N drain. In some embodiments, the III-N transistors are disposed over a silicon substrate. In some embodiments, lateral epitaxial overgrowth is employed to form III-N islands self-aligned with the vertically-oriented drift region. A gate electrode disposed over a portion of a III-N island may modulate a 2DEG within a channel region of the III-N island disposed above the III-N drift region. Charge carriers in the 2DEG channel may be swept into the drift region toward the drain. Topside contacts to each of the gate, source, and drain may be pitch scaled independently of a length of the drift region.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic
  • Patent number: 10642080
    Abstract: A display device includes a first substrate defining a top surface thereof, a bottom surface thereof facing the top surface, and side surfaces thereof connecting the top and bottom surfaces to each other. The side surfaces included: a first side surface defined by: a first patterned surface including a first pattern of which a length thereof extends in a diagonal direction in a plan view of the first patterned surface, and a second patterned surface which extends obliquely from an upper end of the first patterned surface, the second patterned surface including a second pattern of which a length thereof extends in a perpendicular direction from the upper end of the first patterned surface in a plan view of the second patterned surface.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Se Ki Park, Joo Young Kim, Dong Rak Ko, Young Woon Kho, Dong Kwon Kim, June Hyoung Park, Eun Ji Seo, Hee Kyun Shin, Seung Je Lee
  • Patent number: 10636887
    Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes laterally forming a spacer on a side of the semiconductor structure. The method further includes performing a thermal anneal on the semiconductor structure. The method further includes performing an etch to remove materials formed by the thermal anneal.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10629600
    Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-jung Kim, Sung-hee Han, Ki-seok Lee, Bong-soo Kim, Yoo-sang Hwang
  • Patent number: 10622459
    Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
  • Patent number: 10615229
    Abstract: A display device includes: a substrate including a display area for displaying an image and a peripheral area positioned adjacent to the display area; a plurality of normal pixels disposed within the display area on the substrate, where each normal pixel includes a first transmissive area and a pixel area disposed adjacent the first transmissive area; and a dummy pixel disposed within the display area on the substrate, adjacent to a curved section of the peripheral area, and disposed between the peripheral area and the plurality of pixels. The dummy pixel includes: a second transmissive area; and a wire area disposed adjacent the second transmissive area.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG DISPLAY CO., INC.
    Inventors: Won Se Lee, Dong Wook Kim, Ae Shin, Su Kyoung Kim
  • Patent number: 10615038
    Abstract: The invention belongs to the technical field of semiconductor material preparation, and in particular provides a preparation method of tin doped n-type gallium oxide. To pre-deposit the appropriate tin doping source on gallium oxide materials in proper ways. The gallium oxide material is then placed in a high temperature tube in an appropriate manner. Then the tin atoms can be controlled to diffuse into the gallium oxide material by heat treatment at a certain temperature for a period of time. Then the tin atoms can be activated as an effective donor to realize the n-type doping of the gallium oxide material. In this invention, the doping can be realized after the preparation of the gallium oxide material is completed, and the necessary equipment and process are simple, and the doping controllability is high.
    Type: Grant
    Filed: March 26, 2017
    Date of Patent: April 7, 2020
    Assignee: DALIAN UNIVERSITY OF TECHNOLOGY
    Inventors: Hongwei Liang, Xiaochuan Xia, Heqiu Zhang
  • Patent number: 10607962
    Abstract: A method for manufacturing semiconductor chips (2, 3) having arranged thereon metallic shaped bodies (6), having the following steps: arranging a plurality of metallic shaped bodies (6) on a processed semiconductor wafer while forming a layer arranged between the semiconductor wafer and the metallic shaped bodies (6), exhibiting a first connection material (4) and a second connection material (5), and processing the first connection material (4) for connecting the metallic shaped bodies (6) to the semiconductor wafer without processing the second connecting material (5), wherein the semiconductor chips (2, 3) are separated either prior to arranging the metallic shaped bodies (6) on the semiconductor wafer or after processing the first connection material (4).
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: March 31, 2020
    Assignee: DANFOSS SILICON POWER GMBH
    Inventors: Frank Osterwald, Martin Becker, Holger Ulrich, Ronald Eisele, Jacek Rudzki
  • Patent number: 10608105
    Abstract: A substrate for a metal oxide semiconductor field effect transistor, and a metal oxide semiconductor field effect transistor, are made available. The substrate encompasses: an n-doped epitaxial drift zone, a p?-doped epitaxial first layer disposed on the drift zone, a heavily n-doped second layer disposed on the first layer, and a terminal formed by p+ implantation, the first layer being in electrical contact with the terminal and being disposed laterally between the terminal and a trench, the trench being formed in the drift zone, in the first layer, and in the second layer. The substrate is characterized in that an implantation depth (P) of the p+ implantation is at least as great as a depth of the trench. The deep p+ implantation can separate adjacent trenches in such a way that a field can no longer attack a gate oxide because it is directed around the gate oxide.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: March 31, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Michael Grieb, Achim Trautmann, Ning Qu
  • Patent number: 10593566
    Abstract: A method for manufacturing a switch-mode converter includes forming a plurality of windings by coiling one or more conductors. Each of the windings is secured to one of a plurality of module bases arranged in a module array. At least one side of the array is encapsulated in a magnetic mold compound.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kristen Nguyen Parrish, Charles Devries
  • Patent number: 10593852
    Abstract: A display device is provided. The display device includes a substrate, a plurality of signal lines disposed on the substrate, and a plurality of display units disposed on the substrate. At least one of the signal lines includes a main line, a plurality of first branch lines electrically connected to the main line, and a plurality of second branch lines electrically connected to the main line. At least one of the display units includes a plurality of main pads, a plurality of redundant pads, and a light-emitting device electrically connected to the main pads. At least one of the main pads is electrically connected to at least one first branch line, and at least one of the redundant pads is electrically connected to at least one second branch line.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: March 17, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
  • Patent number: 10586860
    Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Laertis Economikos, Xusheng Wu, John Zhang, Haigou Huang, Hui Zhan, Tao Han, Haiting Wang, Jinping Liu, Hui Zang
  • Patent number: 10580797
    Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: March 3, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10580862
    Abstract: A high-voltage semiconductor device has a main high-voltage switch device and a current-sense device for mirroring the current through the main high-voltage switch device. The main high-voltage switch device has a plurality of switch cells arranged to form a first array on a semiconductor substrate. Each switch cell has a first cell width. The current-sense device has a plurality of sense cells arranged to form a second array on the semiconductor substrate. Each sense cell has a second cell width larger than the first cell width. The switch cells and the sense cells share a common gate electrode and a common drain electrode.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: March 3, 2020
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Wan Wen Tseng, Jen-Hao Yeh, Yi-Rong Tu, Chin-Wen Hsiung
  • Patent number: 10573622
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Lilia May, Edward R. Prack
  • Patent number: 10573724
    Abstract: A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10566258
    Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: February 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kuniharu Muto, Koji Bando
  • Patent number: 10553829
    Abstract: A display device includes a flexible substrate including a first surface and a second surface facing the first surface; a TFT array layer provided on the first surface; a display element layer provided on the TFT array layer; a first heat releasing layer provided on the second surface; a first protective layer provided on the same side as the second surface; a second heat releasing layer provided on the display element layer; and a second protective layer provided on the display element layer. The second heat releasing layer has a light transmittance of 90% or higher.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: February 4, 2020
    Assignee: Japan Display Inc.
    Inventors: Kenta Hiraga, Hajime Akimoto
  • Patent number: 10529898
    Abstract: An optoelectronic element includes an optoelectronic unit, a first metal layer, a second metal layer, a conductive layer and a transparent structure. The optoelectronic unit has a central line in a top view, a top surface, and a bottom surface. The second metal layer is formed on the top surface, and has an extension portion crossing over the central line and extending to the first metal layer. The conductive layer covers the first metal layer and the extension portion. The transparent structure covers the bottom surface without covering the top surface.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 7, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Cheng-Nan Han, Tsung-Xian Lee, Min-Hsun Hsieh, Hung-Hsuan Chen, Hsin-Mao Liu, Hsing-Chao Chen, Ching San Tao, Chih-Peng Ni, Tzer-Perng Chen, Jen-Chau Wu, Masafumi Sano, Chih-Ming Wang
  • Patent number: 10510719
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Meng-Tse Chen, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng