Patents Examined by Ermias T Woldegeorgis
  • Patent number: 12249662
    Abstract: A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: March 11, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Ya-Chin King, Chrong Jung Lin, Burn Jeng Lin, Shi-Jiun Wang
  • Patent number: 12247919
    Abstract: Systems and methods for performing non-destructive sensing of a cell or tissue, in vivo or in culture, are provided. The disclosed systems and methods include fabricating and powering one or more implantable integrated circuit (IC) chips that include a network of Photovoltaic (PV) cells for energy harvesting from an optical energy source, an optical modulator integrating Quantum Dot capacitors (QD-caps) for optical data transfer using fluorescence modulation, and sensing circuitry. The IC chip disclosed herein can measure a thickness of around 10 ?m, allowing injection into small cells and diffusion through tissue, it is powered and imaged under a microscope and communicates using fluorescence modulation imaged under a microscope.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: March 11, 2025
    Inventors: Kenneth L. Shepard, Girish Ramakrishnan
  • Patent number: 12249542
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 12247043
    Abstract: Provided are spiro-bisilepine compounds. Also provided are formulations comprising these spiro-bisilepine compounds. Further provided are OLEDs and related consumer products that utilize these spiro-bisilepine compounds.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: March 11, 2025
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Tyler Fleetham, Suman Layek
  • Patent number: 12243694
    Abstract: [Problem] To provide a method for manufacturing an element which does not lead to the occurrence of a short due to etching, and which suppresses the deterioration of a photoelectric conversion layer.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 4, 2025
    Assignee: EneCoat Technologies Co., Ltd.
    Inventors: Tsuyoshi Takahama, Toshihiko Yabumoto
  • Patent number: 12224332
    Abstract: The purpose of the present invention is to suppress a change in characteristics of a TFT using an oxide semiconductor film caused by that oxygen in the oxide semiconductor film is extracted by metal electrode. The main structure of the present invention is as follows. A semiconductor device having a TFT, in which a gate insulating film is formed on a gate electrode, and an oxide semiconductor film is formed on the gate insulating film; the oxide semiconductor film including a channel region, a drain region, and a source region; in which a metal nitride film is formed on a top surface of the gate electrode in an opposing portion to the channel region in a plan view; and the metal nitride film is not formed at a part of the top surface of the gate electrode.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 11, 2025
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Takuo Kaitoh, Hajime Watakabe
  • Patent number: 12224100
    Abstract: A coil component includes a support substrate having one surface including at least one groove portion; a coil portion disposed to contact the one surface of the support substrate; and a body embedding the support substrate and the coil portion, wherein the coil portion has an anchor portion disposed in the at least one groove portion, and a pattern portion disposed on the anchor portion and spaced apart from the one surface of the support substrate. A line width of the anchor portion is narrower than a line width of the pattern portion.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: February 11, 2025
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Hun Kim, Byeong Cheol Moon, Joung Gul Ryu
  • Patent number: 12219766
    Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: February 4, 2025
    Assignee: Kioxia Corporation
    Inventors: Masaki Tsuji, Yoshiaki Fukuzumi
  • Patent number: 12218126
    Abstract: The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: February 4, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qian Xu
  • Patent number: 12219787
    Abstract: The present invention provides QLED devices, hole transport materials and producing methods thereof, and display devices. A hole transport material includes a polymer, wherein the polymer is a single nanoparticle including at least a first metal compound and a second metal compound, the first metal compound and the second metal compound are linked via a covalent bond or a Van der Waals force, and valence band energy levels of the first metal compound and the second metal compound are different.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 4, 2025
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Jingwen Feng
  • Patent number: 12204232
    Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Shu Huang, Ming Chyi Liu, Tung-He Chou
  • Patent number: 12198846
    Abstract: An inductor device includes a first wire, a second wire, a third wire, a fourth wire and an 8-shaped inductor structure. The first wire is disposed in a first area. The second wire is disposed in a second area. The third wire is disposed in the first area and at least partially overlapped with the first wire in a vertical direction. The third wire includes at least two third sub-wires, and the at least two third sub-wires are arranged with an interval between each other. The fourth wire is at least partially overlapped with the second wire in the vertical direction. The fourth wire includes at least two fourth sub-wires, and the at least two fourth sub-wires are arranged with an interval between each other. The eight-shaped inductor structure is disposed on an outer side of the third wire and the fourth wire.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 14, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 12201006
    Abstract: A display device including a display panel and a support layer is provided. The display panel has a light-transmitting area and a bonding area connected to the light-transmitting area. The support layer includes a first support layer and a second support layer, where the first support layer has a first portion corresponding to the light-transmitting area, the second support layer has a second portion corresponding to the bonding area, and an optical phase retardation coefficient of the first portion is less than an optical phase retardation coefficient of the second portion.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 14, 2025
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Yunti Zhang, Dong Zhan, Hanning Yang, Xin Liu
  • Patent number: 12185622
    Abstract: A color conversion composition that converts incident light into light having a longer wavelength than the incident light is described, the color conversion composition including the following components (A) and (B): component (A): an organic light-emitting material; and component (B): a resin whose molecular structure has a fluorene skeleton.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 31, 2024
    Assignee: Toray Industries, Inc.
    Inventors: Kana Kawahara, Tatsuya Kanzaki
  • Patent number: 12185642
    Abstract: A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising an elastic material and a superconductor film, releasing a portion of the elastic material by selective removal of the release film so that portion lifts out of the substrate plane to form elastic springs. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising at least an elastic material, releasing a portion of the elastic material so that portion lifts out of a plane of the substrate to form elastic springs, and coating the elastic springs with a superconductor film.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: December 31, 2024
    Assignee: Xerox Corporation
    Inventors: Christopher L. Chua, Eugene M. Chow
  • Patent number: 12183590
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Patent number: 12156473
    Abstract: Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Nicholas James Harold McKubre, Han Wui Then
  • Patent number: 12151213
    Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Ang Chao, Gregory Michael Pitner, Tse-An Chen, Lain-Jong Li, Yu Chao Lin
  • Patent number: 12150302
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: November 19, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ramy Nashed Bassely Said, Senaka Kanakamedala, Raghuveer S. Makala, Peng Zhang, Yanli Zhang
  • Patent number: 12150375
    Abstract: Provided are a dipolar molecule-stabalized perovskite material and an optoelectronic device. The invention aims to provide the perovskite material with the stable dipolar molecules and the optoelectronic device, which can indirectly enhance an interaction between metal cations and halogen anions, reduce a defect state density in the perovskite material, and inhibit ion migration in the perovskite material by utilizing dipolar groups in a dipolar molecule stabilizer. A component of the perovskite material with the stable dipolar molecules is D: A? 2An-1BnX3n+1 or D: ABX3, wherein A? is an organic amine cation, A is a monovalent cation, B is a metal cation, X is a monovalent anion, and D is the dipolar molecule stabilizer. A thermal stability, a phase stability and a photoluminescence stability of the material are remarkably enhanced, and working stabilities and efficiencies of the perovskite material and the optoelectronic device are remarkably improved.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: November 19, 2024
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Dawei Di, Bingbing Guo, Yaxiao Lian, Baodan Zhao