Patents Examined by Ermias T Woldegeorgis
  • Patent number: 10991722
    Abstract: One silicon MOSFET transistor, which is used as the VThreshold control, and a GaN power HEMT are integrated on a single die to enable a fully integrated depletion-mode power device. GaN area is created on a silicon substrate and GaN FETs are built in the GaN area. Outside of the GaN area, silicon transistors such as switch MOSFETs are built. Front end of line or back end of line metal connections are then made to create interconnections among the GaN FET and the silicon transistor. The short physical proximity of the silicon transistor and GaN HEMT significantly reduces the parasitic resistance and inductance between them. Thus, high speed signals are able to travel from the silicon transistor to the GaN HEMT with a higher frequency and lower distortion, without creating overshoot voltage when there is large parasitic inductance. Therefore, the cascode device can operate at a higher switching frequency.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ko-Tao Lee, Xin Zhang, Todd E. Takken
  • Patent number: 10985009
    Abstract: Embodiments include a method for forming a carbon containing film. In an embodiment, the method comprises flowing a precursor gas into a processing chamber. For example the precursor gas comprises carbon containing molecules. In an embodiment, the method further comprises flowing a co-reactant gas into the processing chamber. In an embodiment, the method further comprises striking a plasma in the processing chamber. In an embodiment plasma activated co-reactant molecules initiate polymerization of the carbon containing molecules in the precursor gas. Embodiments may also include a method that further comprises depositing a carbon containing film onto a substrate in the processing chamber.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 20, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Lakmal Charidu Kalutarage, Mark Saly, David Thompson, William John Durand, Kelvin Chan, Hanhong Chen, Philip Allan Kraus
  • Patent number: 10978615
    Abstract: The present disclosure provides a light-emitting apparatus comprising a board having a plurality of first metal contacts and a plurality of second metal contacts on a top surface; a plurality of LEDs being bonded to the board, the each of the LEDs comprising a first cladding layer on the substrate, an active layer on the first cladding layer, a second cladding layer on the active layer, an upper surface on the second cladding layer, a first metal layer, and a second metal layer, wherein the first metal layer and the second metal layer are between the active layer and the board; an opaque layer between the adjacent LEDs and comprising a polymer mixed with a plurality of inorganic particles; and an encapsulating layer on the upper surfaces and opposite to the board, wherein the encapsulating layer does not cover a side wall of the active layer; and an underfill material between the board and the plurality of LEDs, wherein the underfill material surrounds each of the first metal layer and the second metal layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: April 13, 2021
    Assignee: Epistar Corporation
    Inventors: Min-Hsun Hsieh, Tzer-Perng Chen, Jen-Chau Wu, Yuh-Ren Shieh, Chuan-Cheng Tu
  • Patent number: 10964842
    Abstract: The present invention relates to an electrode assembly comprising nano-scale-LED elements and a method for manufacturing the same and, more specifically, to an electrode assembly comprising nano-scale-LED elements and a method for manufacturing the same, in which the number of nano-scale-LED elements included in a unit area of the electrode assembly is increased, the light extraction efficiency of individual nano-scale-LED elements is increased so as to maximize light intensity per unit area, and at the same time, nano-scale-LED elements on a nanoscale are connected to an electrode without a fault such as an electrical short circuit.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: March 30, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yeon Goog Sung
  • Patent number: 10957857
    Abstract: The present specification relates to a multicyclic compound and an organic light-emitting device including the same. The multicyclic compound of Chemical Formula 1 used in one or more organic material layers of the organic light emitting device provides enhanced efficiency, decreased driving voltage and enhanced lifespan property of the organic light emitting device.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: March 23, 2021
    Assignee: LG CHEM LTD.
    Inventors: Yongbum Cha, Sang Young Jeon, Sung Jae Lee, Sung Kil Hong
  • Patent number: 10957722
    Abstract: A method of manufacturing a flexible device includes joining a first surface of a support substrate to a back surface of a flexible substrate, the first surface being opposite to a second surface of the support substrate; forming an element layer on a front surface of the flexible substrate; and performing multidirectional oblique irradiation of an interface and its vicinity between the support substrate and the flexible substrate with laser light from the second surface of the support substrate to detach the support substrate from the flexible substrate.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: March 23, 2021
    Assignee: JOLED INC.
    Inventors: Tomoatsu Kinoshita, Takashige Fujimori, Yuichi Kato
  • Patent number: 10950491
    Abstract: A useful layer is layered onto a support by a method that includes the steps of forming an embrittlement plane by implanting light elements into a first substrate, so as to form a useful layer between such plane and one surface of the first substrate; applying the support onto the surface of the first substrate so as to form an assembly to be fractured; applying a heat treatment for embrittling the assembly to be fractured; and initiating and propagating a fracture wave into the first substrate along the embrittlement plane. The fracture wave is initiated in a central area of the embrittlement plane and the propagation speed of the wave is controlled so that the velocity thereof is sufficient to cause the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof, if any, are confined to a peripheral area of the useful layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: March 16, 2021
    Assignees: Soitec, COMMISSARIAT Á L'ÈNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frederic Mazen, Damien Massy, Shay Reboh, Francois Rieutord
  • Patent number: 10943816
    Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, and patterning the hardmask layer into a plurality of hardmask portions. The method also includes forming a liner layer on the plurality of hardmask portions, and removing a portion of the liner layer from at least one hardmask portion of the plurality of hardmask portions. The removing exposes one or more surfaces of the at least one hardmask portion. In the method, the at least one hardmask portion and a remaining portion of the liner layer are removed. A pattern of remaining ones of the plurality of hardmask portions are transferred to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, ChoongHyun Lee
  • Patent number: 10937697
    Abstract: A method of processing a wafer includes a cutting step of cutting the face side of the wafer with a cutting blade to form grooves therein along projected dicing lines, a first inspecting step of capturing an image of the grooves formed in the cutting step and inspecting a state of a chip in the captured image of the grooves, a protecting member sticking step of sticking a protective member to the face side of the wafer, a grinding step of holding the protective member side of the wafer on a chuck table and grinding a reverse side of the wafer to thin the wafer to a finished thickness, thereby dividing the wafer into device chips, a second inspecting step of capturing an image of the grooves exposed on the reverse side of the wafer and inspecting a state of a chip in the captured image of the grooves.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 2, 2021
    Assignee: DISCO CORPORATION
    Inventor: Tetsukazu Sugiya
  • Patent number: 10937708
    Abstract: A power module that can realize insulation performance by suppressing the occurrence of bubbles in silicone gel and the detachment between the silicone gel and an insulating substrate during high temperature, during low temperature and during low atmospheric pressure, to thereby suppress degradation of insulation performance. The power module includes: an insulating substrate having a front surface on which a power semiconductor element is mounted; a base plate joined to a back surface of the insulating substrate; a case fixed to the base plate and surrounding the insulating substrate; a cover fixed to the case and forming a sealed region; and a silicone gel serving as a filling member filling the entire sealed region and having internal stress maintained at compressive stress.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 2, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masaki Taya
  • Patent number: 10928693
    Abstract: An array substrate, a repair method of the array substrate, a display panel and a display device are provided. The array substrate includes a base substrate, and a common electrode layer, a common electrode line mesh, a first metal layer and a second metal layer which are on the base substrate, and the common electrode line mesh is electrically connected with the common electrode layer. The first metal layer includes a first signal line extending along a first direction; the second metal layer includes a second signal line extending along a second direction and a plurality of repair connection portions; and each repair connection portion has a first overlap portion overlapping the first signal line and a second overlap portion overlapping the common electrode line mesh.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 23, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Lu Che, Qiangqiang Ji, Guoquan Liu, Qiang Zhou, Xiaomei Wei
  • Patent number: 10910529
    Abstract: In a method according to embodiments of the invention, for a predetermined amount of light produced by a light emitting diode and converted by a phosphor layer comprising a host material and a dopant, and for a predetermined maximum reduction in efficiency of the phosphor at increasing excitation density, a maximum dopant concentration of the phosphor layer is selected.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 2, 2021
    Inventors: Peter Josef Schmidt, Oleg Borisovich Shchekin, Walter Mayr, Hans-Helmut Bechtel, Danielle Chamberlin, Regina Mueller-Mach, Gerd Mueller
  • Patent number: 10903135
    Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 26, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: HuiLi Fu, Shujie Cai, Xiao Hu
  • Patent number: 10896943
    Abstract: A display device is disclosed. In one aspect, the display device includes a flexible substrate including a first region, a second region separated from the first region, and a bending region positioned between the first and second regions. The bending region is configured to be bent so as to have a plurality of different curvatures depending on degrees of bending of the flexible substrate. The display device also includes a first display unit positioned in the first region, a second display unit separated from the first display unit and positioned in the second region and an encapsulation layer positioned over the flexible substrate with the first and second display units interposed therebetween. The encapsulation layer directly contacts the bending region of the flexible substrate.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Min-Sung Kim, Thanh Tien Nguyen, Jae Seob Lee, Ki Ju Im
  • Patent number: 10896911
    Abstract: A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 19, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Hsu-Chi Cho, Cheng-Ta Yang
  • Patent number: 10896849
    Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 19, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidehiko Karasaki, Shogo Okita, Noriyuki Matsubara, Hidefumi Saeki
  • Patent number: 10886176
    Abstract: Self-aligned interconnect patterning for back-end-of-line (BEOL) structures is described. A method of fabricating an interconnect structure for an integrated circuit includes depositing a first metal layer on an initial interconnect structure, forming a patterned spacer layer containing recessed features on the first metal layer, and etching a self-aligned via in the first metal layer and into the initial interconnect structure using a recessed feature in the patterned spacer layer as a mask. The method further includes filling the via in the first metal layer and the recessed features in the patterned spacer layer with a second metal layer, removing the patterned spacer layer, and etching a recessed feature in the first metal layer using the second metal layer as a mask.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 5, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Yuki Kikuchi, Kaoru Maekawa
  • Patent number: 10879134
    Abstract: Techniques are disclosed for monolithic co-integration of silicon (Si)-based transistor devices and III-N semiconductor-based transistor devices over a commonly shared semiconductor substrate. In accordance with some embodiments, the disclosed techniques may be used to provide a silicon-on-insulator (SOI) or other semiconductor-on-insulator structure including: (1) a Si (111) surface available for formation of III-N-based n-channel devices; and (2) a Si (100) surface available for formation of Si-based p-channel devices, n-channel devices, or both. Further processing may be performed, in accordance with some embodiments, to provide n-channel and p-channel devices over the Si (111) and Si (100) surfaces, as desired.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 29, 2020
    Assignee: INTEL Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Peter G. Tolchinsky
  • Patent number: 10872987
    Abstract: Barrier infrared detectors having structures configured to enhance the quantum efficiency, and methods of their manufacture are provided. In particular, device structures for constructing high-performance barrier infrared detectors using novel combinations of p-type and n-type absorber regions and contact regions are provided. The infrared detectors generally incorporate a “p+Bpnn+” structure. The detectors generally comprise, in sequence, a highly p-doped contact layer “p+”, an electron unipolar barrier “B”, a p-type absorber section “p”, and n-type absorber section “n”, and a highly n-doped contact layer “n+”.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 22, 2020
    Assignee: California Institute of Technology
    Inventors: David Z. Ting, Alexander Soibel, Arezou Khoshakhlagh, Sarath D. Gunapala
  • Patent number: 10868175
    Abstract: Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. The method includes forming a recess in a substrate and forming an epitaxy region, comprising a multilayer structure with a substance having a first lattice constant larger than a second lattice constant of the substrate. Forming the epitaxy region further includes forming a first layer in proximity to an interface between the epitaxy region and the substrate with an average concentration of the substance from about 20 to about 32 percent by an in situ growth, and forming a second layer over the first layer, a bottom portion of the second layer having a concentration of the substance from about 27 percent to about 37 percent by an in situ growth operation.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu