Abstract: In a method according to embodiments of the invention, for a predetermined amount of light produced by a light emitting diode and converted by a phosphor layer comprising a host material and a dopant, and for a predetermined maximum reduction in efficiency of the phosphor at increasing excitation density, a maximum dopant concentration of the phosphor layer is selected.

Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Abstract: In a method of manufacture, a displacement sensor is provided over a conditioner disk. The conditioner disk is rotated to perform a conditioning process on a polishing surface of a polishing pad. A displacement of the rotating conditioner disk is detected using the displacement sensor during the conditioning process. A height of the conditioner disk is calculated from the detected displacement. An end point of the conditioning process is determined on the polishing surface based on the calculated height.

Abstract: A method of fabricating a device, comprising forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited. The shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.

Abstract: A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.

Abstract: A system includes a substrate support on which to receive a transparent substrate, a non-contact sensor adapted to detect and image a dot pattern etched on a front surface of the transparent substrate, and a processing device attached to the non-contact sensor. The processing device may determine, using imaging data from the non-contact sensor, an orientation of a right-angled edge of the dot pattern. The processing device may determine, based on the orientation of the right-angled edge, whether a front surface of the transparent substrate is facing up or facing down. The processing device may also direct a robot to transfer the transparent substrate to a processing chamber dependent on whether the front surface of the transparent substrate is facing up or facing down.

Abstract: A temperature adjusting device includes a first member and a flow path. The first member has thereon a first surface as a temperature control target. The flow path is formed within the first member along the first surface. A first end of the flow path serves as an inlet opening through which a heat transfer medium is introduced and a second end of the flow path serves as an outlet opening through which the heat transfer medium is discharged. The flow path is formed such that a thermal resistance between the first surface and the flow path increases as the flow path goes from the outlet opening toward the inlet opening.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a first electrode located on the base substrate and including a pad portion, the pad portion including a first surface and a second surface, the second surface being closer to the base substrate than the first surface; a first insulation layer located on the first electrode and including a first via hole; a second insulation layer located on the first insulation layer and including a second via hole; and a second electrode located on the second insulation layer; the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the pad portion on the base substrate falls within an orthographic projection of the second via hole on the base substrate.

Abstract: The present invention relates to an electrode assembly comprising nano-scale-LED elements and a method for manufacturing the same and, more specifically, to an electrode assembly comprising nano-scale-LED elements and a method for manufacturing the same, in which the number of nano-scale-LED elements included in a unit area of the electrode assembly is increased, the light extraction efficiency of individual nano-scale-LED elements is increased so as to maximize light intensity per unit area, and at the same time, nano-scale-LED elements on a nanoscale are connected to an electrode without a fault such as an electrical short circuit.

Abstract: A method for forming at least part of a quantum information processing device is presented. The method includes providing a first electrically-conductive layer formed of a first electrically-conductive material (100?) on a principal surface of a substrate (10), depositing a layer of dielectric material on the first electrically-conductive material, patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer, depositing a second electrically-conductive layer (104?) on the pad of dielectric material and on the first region of the first electrically-conductive layer, patterning the second electrically-conductive layer and removing the pad of dielectric material using isotropic gas phase etching.

Abstract: A photoelectric conversion element of the present disclosure includes a first electrode, a second electrode disposed to be opposed to the first electrode, and an organic photoelectric conversion layer provided between the first electrode and the second electrode and including at least one of a Chryseno[1,2-b:8,7-b?]dithiophene (ChDT1) derivative represented by the general formula (1) or a Chryseno[1,2-b:7,8-b?]dithiophene (ChDT2) derivative represented by the general formula (2).

Abstract: A display device includes a substrate including a display area including a plurality of pixels and a non-display area positioned around the display area and including a bending portion. A first protection layer is at one surface of the bending portion and a second protection layer entirely covers one surface of the bending portion, the second protection layer being positioned outermost of the substrate and the first protection layer based on a center of a curvature radius of the bending portion. The second protection layer is thinner than the first protection layer. The second protection layer has at least one end portion which directly contacts the substrate.

Abstract: Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area of the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface.

Abstract: A semiconductor device includes a trench-type switching element formed in an active region and a trench-type current sense element formed in a current sense region. Below a trench in which a gate electrode of the switching element is embedded, a trench in which a gate electrode of the current sense element is embedded, and a trench formed at the boundary portion between the active region and the current sense region, protective layers are formed, respectively. The protective layer at the boundary portion between the active region and the current sense region has a divided portion that is divided in a direction from the active region to the current sense region.

Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). The single-photon avalanche diodes may be arranged in an array of microcells (such as a silicon photomultiplier). Each microcell may have an aspect ratio that is greater than 1. Each microcell may be covered by a microlens that also has an aspect ratio that is greater than 1. The microlens may have curvature in a first direction (parallel to the width of the microcell/microlens) and less curvature in a second direction that is orthogonal to the first direction (parallel to the length of the microcell/microlens). Forming non-square, rectangular microcells and microlenses in this fashion may allow for larger microcells that still have satisfactory microlens performance.

Abstract: An x-ray detector can be small and have efficient cooling. In one embodiment, the x-ray detector can comprise a thermoelectric cooler (TEC) with upper electrical connections, a support, a cap, and a silicon drift detector (SDD). A planar side of the support can be directly affixed to upper electrical connections of the TEC. The support can have a non-planar side, opposite of the planar side, with a raised structure. A bottom face of the cap can be affixed to the raised structure, forming a cavity between the cap and the non-planar side of the support. The SDD can be affixed to a top face of the cap. In another embodiment, the non-planar side of the support can face the TEC. In another embodiment, a PIN photodiode can be directly affixed to a plate and the plate directly affixed to upper electrical connections of the TEC.

Abstract: An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

Abstract: Provided are a substrate storage apparatus and a substrate processing apparatus using the substrate storage apparatus. The substrate storage apparatus includes a housing having a loading/unloading port for loading/unloading of a substrate and configured to provide a loading space for a loaded substrate, a separation membrane coupled to the housing to divide the loading space into a plurality of separation spaces isolated from each other, a gas supplier configured to supply a purge gas into the loading space to clean the substrate, a gas discharger configured to discharge the purge gas accommodated in the loading space, and a controller configured to control supply and discharge of the purge gas for each of the plurality of separation spaces.

Abstract: A substrate aligning method includes receiving a substrate by moving a substrate support from an outside of an outer periphery toward a central portion of the substrate along the substrate; and aligning the substrate such that the substrate support moves from a position different from a position partially upwardly warped along an outer peripheral edge of the substrate and a position partially downwardly warped along the outer peripheral edge of the substrate toward the central portion of the substrate so as to receive the substrate.