Abstract: A semiconductor device for flame detection, including: a semiconductor body having a first conductivity type conductivity, delimited by a front surface and forming a cathode region; an anode region having a second conductivity type conductivity, which extends within the semiconductor body, starting from the front surface, and forms, together with the cathode region, the junction of a photodiode that detect ultraviolet radiation emitted by the flames; a supporting dielectric region; and a sensitive region, which is arranged on the supporting dielectric region and varies its own resistance as a function of the infrared radiation emitted by the flames.

Abstract: Various embodiments of the present invention provide for a light emitting devices comprising a light emitting layer comprising an electroluminescent organic material dispersed in a matrix, wherein the electroluminescent organic material has a molecular weight less than about 2000 amu, the matrix comprises a nonelectroluminescent-nonpolymeric amorphous glass mixture, and each of the nonelectroluminescent-nonpolymeric organic molecular glass mixture and the electroluminescent organic material constitutes at least 20 percent by weight of the light emitting layer; and electrodes in electrical communication with the light emitting layer and configured to conduct an electric charge through the light emitting layer such that the light emitting layer emits light.

Abstract: A light emitting device includes: a substrate; a first electrode disposed on the substrate; a first insulating layer disposed on the substrate to be spaced apart from the first electrode, the first insulating layer having a first height; a second electrode disposed on the first insulating layer; and a bar type LED disposed on the substrate, wherein the bar type LED has a first end and a second end in the length direction thereof, one of the first end and the second end is connected to the first electrode, and the other of the first end and the second end is connected to the second electrode.

Abstract: A ceramic green wavelength conversion element (120) is coated with a red wavelength conversion material (330) and placed above a blue light emitting element (110) such that the ceramic element (120) is attached to the light emitting element (110), thereby providing an efficient thermal coupling from the red and green converters (330, 120) to the light emitting element (110) and its associated heat sink. To protect the red converter coating (330) from the effects of subsequent processes, a sacrificial clear coating (340) is created above the red converter element (330). This clear coating (340) may be provided as a discrete layer of clear material, or it may be produced by allowing the red converters to settle to the bottom of its suspension material, thereby forming a converter-free upper layer that can be subjected to the subsequent fabrication processes.

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.

Abstract: Performance and reliability of a semiconductor device are improved. An insulating film is formed such that a control gate electrode, a memory gate electrode, and a gate electrode are embedded, and then tops of the control gate electrode, the memory gate electrode, and the gate electrode are exposed by first polishing. Subsequently, a trench is formed by removing the gate electrode and filled with a metal film, and second polishing is performed to form a gate electrode including the metal film. The insulating film is an O3-TEOS film having a high gap filling characteristic, and thus reduces formation of a seam in the insulating film. Furthermore, the O3-TEOS film is subjected to heat treatment in an oxidizing atmosphere before the first polishing, thereby dishing of the insulating film is reduced during the second polishing.

Abstract: A method for manufacturing a semiconductor device comprises forming a first diffusion stop layer on a bulk semiconductor substrate, forming a doped semiconductor layer on the first diffusion stop layer, forming a second diffusion stop layer on the doped semiconductor layer, forming a fin layer on the doped semiconductor layer, patterning the first and second diffusion stop layers, the doped semiconductor layer, the fin layer and a portion of the bulk substrate, oxidizing the doped semiconductor layer to form an oxide layer, and forming a dielectric on the bulk substrate adjacent the patterned portion of the bulk substrate, the patterned first diffusion stop layer and the oxide layer.

Abstract: A semiconductor device has a semiconductor substrate including a first conductivity-type drift layer, a second conductivity-type base layer disposed in a surface layer portion of the drift layer, and a second conductivity-type collector layer and a first conductivity-type cathode layer disposed opposite to the base layer with respect to the drift layer. In the semiconductor substrate, an IGBT region and a diode region are alternately and repetitively arranged. The IGBT region and the diode region are divided by a boundary between the collector layer and the cathode layer. The collector layer is defined as a first collector layer. The semiconductor device includes a second collector layer having a second conductivity-type impurity concentration higher than that of the first collector layer, at a surface of the semiconductor substrate adjacent to the first collector layer and the cathode layer.

Abstract: Method of making a transistor, comprising the following steps: make a gate and a first spacer on a first channel region of a first crystalline semiconducting layer; make first crystalline semiconductor portions on the second source and drain regions; make the second regions amorphous and dope them; recrystallise the second regions and activate the dopants present in the second regions; remove the first portions; make a second spacer thicker than the first spacer; make second doped crystalline semiconductor portions on the second regions, said second portions and the second regions of the first layer together form the source and drain of the transistor.

Abstract: According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance layer, a plurality of vertical channels on the channel layer, and a plurality of gate lines. The vertical channels extend in a first direction that is perpendicular with respect to a top surface of the channel layer. The gate lines surround outer sidewalls of the vertical channels, and are stacked in the first direction and are spaced apart from each other.

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.

Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.

Abstract: Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

Abstract: An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

Abstract: A device having a conductive feature disposed on a substrate; a cap structure is disposed on top of the conductive feature and on at least two sidewalls of the conductive feature. An air gap cap disposed on the cap structure and defines an air gap adjacent the conductive feature.

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

Abstract: A display device includes a first substrate defining a top surface thereof, a bottom surface thereof facing the top surface, and side surfaces thereof connecting the top and bottom surfaces to each other. The side surfaces included: a first side surface defined by: a first patterned surface including a first pattern of which a length thereof extends in a diagonal direction in a plan view of the first patterned surface, and a second patterned surface which extends obliquely from an upper end of the first patterned surface, the second patterned surface including a second pattern of which a length thereof extends in a perpendicular direction from the upper end of the first patterned surface in a plan view of the second patterned surface.

Abstract: The reliability of a transistor including an oxide semiconductor is improved. The transistor in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region overlapping with the second oxide semiconductor film, a source region and a drain region each in contact with the second insulating film. The channel region includes a first layer and a second layer in contact with a top surface of the first layer and covering a side surface of the first layer in the channel width direction. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.

Abstract: The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) layer over the bottom electrode, a top electrode over the MTJ layer, and a (N+1)th metal layer over the top electrode. The top electrode includes material having an oxidation rate lower than that of Tantalum or Tantalum derivatives. N is an integer greater than or equal to 1.