Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

Abstract: Disclosed are methods for manufacturing semiconductor devices and the devices thus obtained. In one embodiment, the method comprises obtaining a semiconductor substrate comprising a germanium region doped with n-type dopants at a first doping level and forming an interfacial silicon layer overlying the germanium region, where the interfacial silicon layer is doped with n-type dopants at a second doping level and has a thickness higher than a critical thickness of silicon on germanium, such that the interfacial layer is at least partially relaxed. The method further includes forming over the interfacial silicon layer a layer of material having an electrical resistivity smaller than 1×10?2 ?cm, thereby forming an electrical contact between the germanium region and the layer of material, wherein the electrical contact has a specific contact resistivity below 10?4 ?cm2.

Abstract: A light-emitting diode and method of manufacturing the same, including a flat portion and a mesa structure including an inclined side surface formed by wet etching and a top surface. A protective film and an electrode film sequentially cover a part of the flat portion and at least a part of the mesa structure, the protective film including an electrical conduction window arranged around a light emission hole and from which a compound semiconductor layer is exposed. The electrode film is a continuous film that contacts the surface of the exposed compound semiconductor layer, covers a portion of the protective film formed on the flat portion, and has the light emission hole on the top surface. A transparent film is formed between a reflecting layer and a compound semiconductor layer. A through-electrode is provided in a range of the transparent film which overlaps the light emission hole.

Abstract: A nonvolatile memory device comprises a substrate, a gate electrode, a single charge trapping sidewall and a source/drain region. The gate electrode is disposed on and electrically isolated from the substrate. The single charge trapping sidewall is disposed adjacent to a sidewall of the gate electrode and electrically isolated from the substrate and the gate electrode, so as to form a non-straight angle between the substrate and the single charge trapping sidewall. The source/drain region is disposed in the substrate and adjacent to the gate electrode.

Abstract: A semiconductor device includes an N-type semiconductor region, a back electrode, first and second P-type base regions, first and second N+ diffusion layers, a gate insulating film, a gate electrode and a voltage detecting circuit. The first N+ diffusion layer functions as a source of an output MOS transistor and functions as a source of a sense MOS transistor. The gate electrode is provided to oppose the N-type semiconductor region and the first and second P-type base regions through the gate insulating film 40. A load current flows between the back electrode and the first N+ diffusion layer. The voltage detecting circuit generates a detection signal.

Abstract: In one embodiment a semiconductor package includes a metal lid configured as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to a metalized area located on the surface of the active circuitry, or to an additional metalized die. Appropriate interconnect methods between the lid and the metalized die or metalized area include, but are not restricted to, wire bonding, bumps, tabs, or similar techniques.

Abstract: A semiconductor light emitting device according to an embodiment includes a top layer having a top surface and a bottom surface, the top layer being an n electrode; an uneven pattern formed in the bottom surface of the n electrode; an n-type semiconductor layer formed under the n electrode, the n-type semiconductor layer having a top surface and a bottom surface; an uneven pattern formed in the top surface of the n-type semiconductor layer, the uneven pattern of the n-type semiconductor layer corresponding to the uneven pattern of the n electrode; an active layer formed under the n-type semiconductor layer; a p-type semiconductor layer formed under the active layer; and a p electrode formed under the p-type semiconductor layer.

Abstract: An optoelectronic element includes an optoelectronic unit having a first top surface; a first metal layer on the first top surface; a first transparent structure surrounding the optoelectronic unit and exposing the first top surface; and a first contact layer on the first transparent structure, including a connective part electrically connected with the first metal layer.

Abstract: Embodiments of the invention include a plurality of semiconductor light emitting diodes attached to a mount. A plurality of lenses are disposed over the plurality of semiconductor light emitting diodes. A lens disposed over a semiconductor light emitting diode proximate an edge of the mount is rotationally asymmetrical and is shaped such that for a portion of the lens light emitted at an intensity that is half a maximum intensity is emitted at an angle of at least 70° relative to a normal to a top surface of the semiconductor light emitting diode.

Abstract: A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate.

Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.

Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.

Abstract: According to one embodiment, a method of manufacturing a solid-state imaging device includes a trench forming process, a concave portion forming process, a coating process, and a burying process. In the trench forming process, a trench is formed at the position to isolate a plurality of photoelectric conversion elements. In the concave portion forming process, a concave portion is formed at the position to form a light shielding film of shielding at least part of subject light incident on an adjustment photoelectric conversion element used for an image quality adjustment of an imaged image. In the coating process, inner circumferential surfaces of the trench and the concave portion are coated with an insulating film. In the burying process, a light shielding member is buried inside the trench and the concave portion whose inner circumferential surface are coated with the insulating film.

Abstract: Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.

Abstract: A semiconductor optical emitting device comprises an at least partially transparent substrate and an active semiconductor structure arranged on a first side of the substrate. A first portion of light generated by the active semiconductor structure is emitted through the substrate from the first side of the substrate to a second side of the substrate along a primary light emission path. The second side of the substrate has a groove formed therein with at least first and second surfaces configured to reflect respective additional portions of the light generated by the active semiconductor structure along respective first and second angled light emission paths. The first and second angled light emission paths may be in opposite directions to one another and substantially perpendicular to the primary light emission path, although numerous other light emission path arrangements are possible.

Abstract: A hybrid substrate includes a core layer composed of a glass woven cloth as a reinforcing material, and a glass-ceramic sintered body which at least has a glass component and a metal oxide component. The glass woven cloth and the glass-ceramic sintered body formed by an impregnation with respect to the glass woven cloth are in a form of sintering integration with each other.

Abstract: A semiconductor light emitting element, includes: a laminated structure body including an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer; a p-side electrode provided in contact with the p-type semiconductor layer; an n-side electrode provided in contact with the n-type semiconductor layer; a highly reflective insulating layer provided in contact with the n-type semiconductor layer and having a higher reflectance than a reflectance of the n-side electrode; and an upper metal layer provided on at least a part of the n-side electrode and on at least a part of the highly reflective insulating layer and electrically connected to the n-side electrode. An area of a region of the n-side electrode in contact with the n-type semiconductor layer is smaller than an area of a region of the highly reflective insulating layer sandwiched between the n-type semiconductor layer and the upper metal layer.

Abstract: A semiconductor device includes a semiconductor element substrate, wherein an electrode pattern is formed on one surface of an insulating substrate and a back-surface electrode is formed on the other surface of the insulating substrate; a stress-relaxation adhesive layer made of resin that covers at least a part of a portion of the surface of the insulating substrate where the electrode pattern and the back-surface electrode are not formed; and a semiconductor element affixed, using a bonding material, to the surface of the electrode pattern opposite the insulating substrate, and a first sealing resin member which covers the semiconductor element and the semiconductor element substrate, and a modulus of elasticity of the stress-relaxation adhesive layer is lower than that of the first sealing resin member.

Abstract: A MEMS device (20) includes a proof mass structure (26) and beams (28, 30) residing in a central opening (32) of the proof mass structure (26), where the structure and the beams are suspended over a substrate (22). The beams (28, 30) are oriented such that lengthwise edges (34, 36) of the beams are beside one another. Isolation segments (38) are interposed between the beams (28, 30) such that a middle portion (40) of each of the beams is laterally anchored to adjacent isolation segments (38). The isolation segments (38) provide electrical isolation between the beams. The beams (28, 30) are anchored to the substrate (22) via compliant structures (61, 65) that isolate the beams from deformations in the underlying substrate. The compliant structures (61, 65) provide electrically conductive paths (96, 98) to the substrate (22) for the beams (28, 30) where the paths are electrically isolated from one another.

Abstract: A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.