Patents Examined by Ernest F. Karlsen
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Patent number: 5903146Abstract: The present invention comprises a system for testing a manufacture. The testing system comprises at least two test means wherein each of the test means is capable of testing at least a performance parameter of the manufacture. The test means are distributed in a production line of the manufacture for performing the tests of the performance parameters on the manufacture.Type: GrantFiled: September 5, 1996Date of Patent: May 11, 1999Assignee: Delta Electronics, Inc.Inventor: Giant Wang
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Patent number: 5903162Abstract: An adapter for a measurement test instrument electrical probe has a flexible dielectric substrate with electrically conductive runs thereon. One end of the conductive runs has first electrical contacts with a pitch geometry corresponding to the pitch geormetry of electrical contacts of an electronic device that is electically connected to a substrate via the electrical contacts of the device. The other end of the conductive runs has second electrical contacts that have a pitch geometry compatible with the electrical probe of the measurement test instrument.Type: GrantFiled: October 14, 1997Date of Patent: May 11, 1999Assignee: Tektronix, Inc.Inventors: Paul A. Cole, Emory J. Harry, Michael A. Wright
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Patent number: 5903161Abstract: An electrically conductive rod-shaped single crystal product, which is a rod-shaped single crystal having an aspect ratio of from 1 to 500, formed by a vapor-liquid-solid method or such a rod-shaped single crystal having its forward end alloy portion removed, wherein at least side surface of said rod-shaped single crystal is coated by an electrically conductive film having a thickness of from 0.1 to 10 .mu.m.Type: GrantFiled: January 26, 1995Date of Patent: May 11, 1999Assignee: Denki Kagaku Kogyo Kabushiki KaishaInventors: Masaru Amemiya, Kazuo Kato, Noriaki Nakazaki, Tatsuo Nakano
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Patent number: 5900737Abstract: A positioner facilitates docking and undocking of an electronic test head with a device handler. The positioner provides for rotation of the test head about a first axis. The positioner includes a linkage arm structure for moving the test head along a second axis orthogonal to the first axis. Using motors, sensors and a processor, the linkage arm structure accurately docks the electronic test head with the device handler.Type: GrantFiled: May 7, 1996Date of Patent: May 4, 1999Assignee: inTEST CorporationInventors: Daniel J. Graham, Alyn R. Holt, Robert E. Matthiessen, I. Marvin Weilerstein, Christopher L. West
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Patent number: 5898314Abstract: A translator fixture for a printed circuit board tester has a pattern of test probes on a base upon which the translator fixture is mounted. The translator fixture includes a plurality of essentially parallel and vertically spaced apart rigid translator plates supported in a fixed position in the translator fixture. Selected patterns of holes are aligned in the translator plates for containing and supporting translator pins extending through the translator plates and for positioning the translator pins for contacting test points under pressure on a printed circuit board supported in an essentially horizontal position between the translator plates. The pins translate electrical test signals between the test points on the printed circuit board and the test probes on the base of the tester. The fixture includes a plurality of blind pins positioned in a top plate of the fixture for non-electrically applying a balancing force to the printed circuit board.Type: GrantFiled: February 26, 1996Date of Patent: April 27, 1999Assignee: Delaware Capital Formation, Inc.Inventor: Mark A. Swart
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Patent number: 5898299Abstract: The hand held circuit tester includes a hollow handle. A probe extends from one end of the handle. First and second leads extend from the other. An LED carrying circuit board is situated within the handle. One end of the circuit board is connected to the probe by a spring. The other end is connected to the leads. A "U" shaped collar is received within slots in the circuit board in a position perpendicular to the plane of the circuit board. The collar edge abuts the edge of one of the handle parts to stabilize the circuit board relative to the handle.Type: GrantFiled: June 21, 1996Date of Patent: April 27, 1999Assignee: S&G Tool Aid Corp.Inventor: Adolph Fodali
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Patent number: 5898312Abstract: A probe head includes analog amplifier inputs, a ground plane, and hundreds of probe leads between the inputs and the pins of a circuit under test. The customer defines the grounded pins of the circuit under test. Non-active probe leads, i.e. leads corresponding to the grounded pins are connected to the ground plane, maximizing the connections between the grounds of the probe and the circuit under test and minimizing unequal ground potentials. The probe circuit is on a probe circuit board, while the connections between the ground plane and the leads are fusible elements on a separate ground personality board. The probe is placed on a simulated circuit under test, the grounded pins on the circuit under test are protected by an insulating cap, and a voltage is placed on the remainder of the pins to fuse the elements corresponding the active probe leads.Type: GrantFiled: April 30, 1997Date of Patent: April 27, 1999Assignee: Hewlett-Packard CompanyInventors: Thomas F. Uhling, David J. Dascher, Keith C. Griggs
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Patent number: 5898311Abstract: A shorting pad probe tip for a substrate tester includes a compliant mandrel, a flexible conductive sheet and a nest plate. The flexible conductive sheet is loosely wrapped around the compliant mandrel. The compliant mandrel and flexible conductive sheet are secured together to the supporting nest plate. At least one side of the flexible conductive sheet is electrically conductive such that when the probe tip is brought in contact with the substrate to be tested, I/O pads on the surface of the substrate become electrically connected. In one embodiment the flexible conductive sheet is metallized polyimide.Type: GrantFiled: December 6, 1996Date of Patent: April 27, 1999Assignee: International Business Machines CorporationInventors: Paul Francis Bodenweber, Robert Charles Polacco, Yuet-Ying Yu
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Patent number: 5896036Abstract: A carrier for testing an unpackaged semiconductor die is provided. The carrier includes: a base; a temporary interconnect for establishing electrical communication between the die and external test circuitry; a retention mechanism for securing the interconnect to the base; and a force distribution mechanism for biasing the die and interconnect together. The interconnect includes a substrate having raised contact members adapted to penetrate bond pads, or tests pads, on the die to form an electrical connection. Conductive traces are formed on the substrate in electrical communication with the raised contact members and connect to external connectors formed on the base. The interconnect is adapted for testing a particular type of die but is interchangeable with other interconnects to permit testing of different types of dice using a universal carrier.Type: GrantFiled: June 10, 1996Date of Patent: April 20, 1999Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree
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Patent number: 5896035Abstract: An electric field measuring apparatus can guide, with a predetermined optical path length, pulse light with a short pulse width output from a laser light source to an object to be measured or an electric field sensor without expansion of the pulse width caused by wavelength dispersion, thereby enabling electric field measurement with a high time resolution. A laser luminous flux incident on an input end of an input optical system is divided by a light dividing section into probe light and pumping light.Type: GrantFiled: January 7, 1997Date of Patent: April 20, 1999Assignee: Hamamatsu Photonics K.K.Inventor: Hironori Takahashi
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Patent number: 5894217Abstract: A test handler decreases an index time in testing IC devices and improves a positioning accuracy for placing the IC devices on a test position of an IC tester. The test handler includes a turn table having a plurality of openings each of which is equally distanced from the other, and at least one of the openings is positioned right above a test socket provided on the IC tester, a plurality of carrier modules attached to the corresponding openings of the turn table where each of the carrier modules has a center opening to receive an IC device to be tested, and a press mechanism provided above the test socket of the IC tester to press the IC device in the carrier module downward so that pins of the IC device contact the test socket.Type: GrantFiled: April 26, 1996Date of Patent: April 13, 1999Assignee: Advantest Corp.Inventors: Noriyuki Igarashi, Kenpei Suzuki
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Patent number: 5894225Abstract: A test fixture for printed circuit boards wherein the circuit board being tested is clamped to a vacuum actuated diaphragm plate by the same vacuum that actuates the diaphragm plate. The vacuum is automatically applied to both the diaphragm plate and the clamp means when the cover on the test fixture is closed. A bridge extends over, and is in clamping contact, with the circuit board. The bridge is supported from platens in vacuum chambers on the upper side of the diaphragm plate.Type: GrantFiled: October 31, 1996Date of Patent: April 13, 1999Inventor: Harry S. Coffin
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Patent number: 5892366Abstract: An adjustable tooling pin for a bed-of-nails test fixture used for testing circuit boards (cards) is provided which allows the tooling pin, and thus the card, to be precisely realigned while the card is still mounted in the test fixture. The adjustable tooling pin mechanism comprises a pivot bushing having a channel running from end-to-end into which a slide bar fits. The tooling pin projects from the end of the sliding bar in the z-direction such that a card may be located over the tooling pin. A locking screw fits through an aperture in the sliding bar and the pivot bushing and is threadably engaged into a threaded insert in the test fixture top plate. Hence, the tooling pin, and thus the card, are radially adjustable in the x-y plane by turning the pivot bushing and by sliding the sliding bar along the pivot bushing channel.Type: GrantFiled: May 24, 1996Date of Patent: April 6, 1999Assignee: International Business Machines CorporationInventor: Rodger A. Byers
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Patent number: 5883521Abstract: A semiconductor device capable of giving glitch noise to a test signal used in a noise test for the device. The semiconductor device includes an input circuit for receiving either a test signal supplied from a device tester or a control signal, and an internal circuit connected to the input circuit by a signal line. The internal circuit operates based on a signal provided from the input circuit. The signal line is connected to a noise generator. The noise generator generates glitch noise in a test signal supplied from the tester.Type: GrantFiled: August 17, 1995Date of Patent: March 16, 1999Assignee: Fujitsu LimitedInventor: Masataka Nishikawa
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Patent number: 5880593Abstract: An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures.Type: GrantFiled: August 30, 1995Date of Patent: March 9, 1999Assignee: Micron Technology, Inc.Inventor: Gary Gilliam
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Method for electrically contacting semiconductor devices in trays and test contactor useful therefor
Patent number: 5872458Abstract: Semiconductor devices (140, 410, 610) are tested or burned-in while in a handling or shipping tray (100, 500, 700) using a test contactor (150, 450, 750, 850, 950) which engages either a cell (120, 520, 720) of the tray or the device itself during testing. A tray having a plurality of devices is moved by a handling system in an initial alignment operation where one or more devices is generally aligned beneath the test contactor. Then, the tray or the test contactor is moved in a vertical direction so that engagement features of the test contactor engage either the tray cell or the device to be tested to bring the device into final alignment for testing. Upon final alignment, contacts (152, 452, 752, 852, 952) of the test contactor physically and electrically contact leads (141, 414, 614) and in-tray testing of the devices is performed. In-tray testing reduces manufacturing cycle and minimizes device lead damage by eliminating pick and place handling of the devices at test.Type: GrantFiled: July 8, 1996Date of Patent: February 16, 1999Assignee: Motorola, Inc.Inventors: Keith Alan Boardman, John Darrell Redden -
Patent number: 5872449Abstract: A multi-sided, integrated circuit die includes a plurality of read only memory (ROM) circuits, positioned only at the corners of the die, to simplify qualification testing of new package designs. During qualification testing, electrical and environmental stresses are applied to the package and die combination. The package and die are electronically evaluated at predetermined intervals to determine whether a failure has occurred during testing. When a failure occurs during testing, the package and die are diagnosed to isolate and determine the cause or source of the failure. Package design parameters are adjusted accordingly to reduce or eliminate the occurrence of the failures. An optional 12-bit counter is fabricated onto the die for each ROM circuit to exercise the ROM during qualification testing. An optional process monitor is also fabricated onto the die for each ROM circuit to determine the strength of the fabrication process and the resulting quality of circuit elements produced therefrom.Type: GrantFiled: June 18, 1997Date of Patent: February 16, 1999Assignee: LSI Logic CorporationInventors: Sudhakar Gouravaram, Wei-Mun Chu, Huy Tran
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Patent number: 5869976Abstract: The apparatus of the present invention includes a frame for attaching the clamp of a hand test socket to a workpress assembly of a high-speed IC handler. The frame attaches to a workpress assembly. Utilizing the clamp of a test socket recycles frequently unused test socket parts and eliminates the need for custom fabricated workpress assembly components. The method for adapting the hand test socket for use on the workpress assembly includes the steps: providing a test socket having a base and a top cover, the top cover including a clamp; removing the top cover and the clamp; configuring the clamp for use in a workpress assembly; and attaching the clamp to the workpress assembly.Type: GrantFiled: December 13, 1996Date of Patent: February 9, 1999Assignee: Cirrus Logic, Inc.Inventors: Mark P. Kelley, Yakov A. Bobrov
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Patent number: 5867034Abstract: A non-destructive method for monitoring the carrier lifetime characteristic of a fabricated semiconductor sample during the fabrication process, where selected materials are deposited on a planar surface of a wafer substrate in a fabrication chamber, employs one or more viewports in the walls of a fabrication chamber, thus avoiding any alteration of the fabrication process. A focused electromagnetic wave is generated external to the fabrication chamber, and directed through a viewport to impinge upon a selected portion of the planar surface of the wafer substrate at an oblique incident angle relative to the planar surface of the wafer substrate. In turn, a reflected electromagnetic wave emanating from the planar surface of the wafer substrate is detected. A light source, also external to the fabrication chamber, generates light directed at the wafer substrate through a viewport. The light is intended to have wavelength components capable of generating hole-electron pairs in the wafer substrate.Type: GrantFiled: January 30, 1997Date of Patent: February 2, 1999Inventors: Vladimir Sokolov, David C. Engelhardt
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Patent number: RE36074Abstract: A particle detector is designed to detect particles such as cells and blood corpuscles, and this particle detector includes means for passing and recovering a multilayer flow consisting of an inner layer A of conductive liquid specimen, a middle layer B of conductive first sheath liquid, and an outer layer C of nonconductive second sheath liquid surrounding them, in an orifice 12, and a pair of electrodes disposed on both sides of the orifice so as to contact the conductive liquid respectively. A detector circuit 44 is connected to the pair of electrodes so as to detect a particle signal on the basis of difference of electric impedance between the electrodes. The diameter of the orifice 12 is substantially the diameter of the middle layer. By varying the flow rate balance of the conductive liquids and nonconductive liquid, the diameter of the middle layer may be freely changed. Accordingly, the diameter of the orifice may be apparently changed as desired.Type: GrantFiled: October 30, 1996Date of Patent: February 2, 1999Assignee: Toa Medical Electronics Co., Ltd.Inventor: Chihiro Kouzuki