Abstract: An inference engine circuit architecture is disclosed which includes a matrix-matrix (MM) processor circuit and a MM accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative MM accelerator circuit includes a first buffer circuit storing maps data; a first data network; multiple second buffer circuits each storing different kernel data; multiple second, serial data networks, with each coupled to a corresponding second buffer circuit; and a plurality of vector-vector (VV) acceleration circuits arranged in a plurality of arrays. Each VV acceleration circuit includes multiply and accumulate circuits; a shift register; a control multiplexer to provide a selected output, in response to a mode control word, of a bias parameter or a first accumulation sum; and a second adder circuit which adds the multiplicative product to the bias parameter or to the first accumulation sum to generate a second or next accumulation sum.

Abstract: Memory operations using compound memory commands, including: receiving, by a memory module, a compound memory command indicating one or more operations to be applied to each portion of a plurality of portions of contiguous memory in the memory module; generating, based on the compound memory command, a plurality of memory commands to apply the one or more operations to each portion of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

Abstract: A memory system includes a memory device including a plurality of memory blocks and a controller suitable for controlling the memory device to store a read retry table that includes a plurality of read bias sets respectively corresponding to a plurality of indexes; controlling the memory device to perform a read retry operation with the read bias sets according to an ascending order of the indexes; updating, when a read operation is successfully performed during the read retry operation, the read retry table by including the read levels of the successful read operation into a read bias set of a highest priority index within the read retry table; and controlling the memory device to perform a subsequent read retry operation based on the updated read retry table.

Abstract: A temporal correlation may be determined between times specified according to different time standards on different storage network components. A host system may poll a storage system periodically. In response to each poll request, the storage system may respond with the current time on the storage system (CST) according to the time standard of the storage system. The host system may store temporal correlation information (TCI) associating the CST and the current time on the host system (CHT) according to the time standard of the host system. A data structure (TCT) may be provided, where each entry may specify TCI for a CST/CHT pair, the TCI including the CST, CHT and other information corresponding to the temporal correlation between the pair. The TCI may be used to correlate the time of a phenomenon according to the host system time standard to a time according to the storage system time standard.

Abstract: A method includes receiving a signal at a memory sub-system controller to perform an operation. The method can further include, in response to receiving the signal, enabling, by the memory sub-system controller, an interface to transfer data to or from a registering clock driver (RCD) component. The RCD component is coupled to the memory sub-system controller. The method can further include transferring the data to or from the RCD component via the interface. The method can further include, in response to the enablement of the interface being unsuccessful, transferring control of a memory device to the memory sub-system controller.

Abstract: Embodiments of the inventive concept include solid state drive (SSD) multi-card adapters that can include multiple solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate evolving solid state drive technologies into servers. The SSD multi-card adapters can include an interface section between various solid state drive cards and drive connector types. The interface section can perform protocol translation, packet switching and routing, data encryption, data compression, management information aggregation, virtualization, and other functions.

Abstract: A transmission control method includes: determining transmission performance in a transmission line by using a parameter that determines a size of an opening of an eye pattern; and adjusting a transmission parameter that is a parameter having an influence on transmission quality in the transmission line on the basis of a result of the determination.

Abstract: An apparatus comprises at least one processing device that is configured to control delivery of input-output operations from a host device to a storage system over selected ones of a plurality of paths through a network. The at least one processing device is further configured to detect a reduction in performance of one or more of the input-output operations over one or more paths of the plurality of paths, to identify a physical initiator component corresponding to the one or more paths, and to notify the storage system about the reduction in performance and the identified physical initiator component. The at least one processing device is also configured to receive a notification from the storage system indicating one or more virtual initiator instances of a plurality of virtual initiator instances corresponding to the identified physical initiator component, and to deactivate the one or more virtual initiator instances.

Abstract: A method for compressing is provided. The method includes compressing, via a processor, a portion of a first data packet to generate a second data packet having a compressed portion. The method includes transmitting the second data packet having the compressed portion via an interface to a co-processor. The processor and the co-processor are communicatively coupled via the interface. The method also includes unpacking, via the co-processor, the compressed portion of the second data packet to restore the first data packet.

Abstract: Peer-to-peer arrangements between graphics processing units (GPUs) are provided herein. A method includes establishing synthetic devices representing GPUs in an address domain associated with a host processor, where the GPUs have a different address domain than the host processor. The method also includes forming a peer arrangement between the GPUs such that data transfers between the GPUs in the different address domain can be initiated by the host processor interfacing with the synthetic devices.

Abstract: A memory system includes a memory controller configured to control an operation of a memory cell array through a first command/address pin and a second other command/address pin and a memory device. The memory device includes a plurality of data pins configured to exchange data input with the memory cell array according to a command/address provided through the first and second command/address pins to the memory controller, a first flip-flop to sample a first command/address signal provided through the first command/address pin as first command/address data at a first time, and a second flip-flop to sample a second command/address signal provided through the second command/address pin as second command/address data at the first time. The memory device provides the first and second command/address data to the memory controller through a first data pin among the plurality of data pins.

Abstract: An information handling system includes a virtual network access module configured to access a virtual network drive that has a first partition in a local storage resource and a second partition in a remote storage resource. In response to detection of an exception, a processor may trigger an exception handler that directs a service processor to initialize a network stack. The processor initializes a mailbox to transmit a mailbox request to retrieve network configuration settings to be used in the initialization of the network stack. The service processor transmits a request to the processor to initialize the mailbox, and initializes the network stack based on the network configuration settings. Subsequent to the initialization of the network stack, a universal network device interface request may be sent to mount and secure communication with the virtual network drive.

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

Abstract: Technologies for efficiently performing memory augmented neural network (MANN) update operations includes a device with circuitry configured to obtain a key usable to search a memory associated with a memory augmented neural network for one or more data sets. The circuitry is also configured to perform a stochastic associative search to identify a group of data sets within the memory that satisfy the key and write to the identified group of data sets concurrently to update the memory augmented neural network.

Abstract: According to an embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate, and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern.

Abstract: A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the event logic. The event broadcast network includes interconnections between the event broadcast circuitry of the DPEs. Detected events can trigger or initiate various responses, such as debugging, tracing, and profiling.

Abstract: Provided are a method of dynamically configuring a FPGA and a network security device. The network security device includes a CPU and at least one FPGA coupled with the CPU. The CPU generates a configuration entry for a target FPGA in response to a user instruction. The configuration entry includes a classification number and a configuration content for the target FPGA. The CPU sends the configuration entry to each FPGA coupled with the CPU, Each FPGA obtains its own classification number, compares its own classification number with the classification number in the configuration entry, and stores the configuration content when the own classification number the same with the classification number in the configuration entry.

Abstract: Embodiments of the present disclosure relate to traffic class management of NVMe (non-volatile memory express) traffic. One or more virtual controllers for at least one host adapter (HA) of a storage device are generated. Each virtual controller is assigned a unique controller identifier (ID) Additionally, one or more input/output (IO) queues for each virtual controller are established. Further, IO workloads are processed via each IO queue.

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

Abstract: A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.