Abstract: A storage system includes a plurality of storage nodes 4 each having one or more storage devices. The storage node includes a CPU. The CPU is configured to select a priority path to be notified as a usable path to a higher-level apparatus among paths which allows access of a predetermined logical unit to which a storage area of the storage device is provided from the higher-level apparatus. The CPU is configured to send the priority path as a reply to an inquiry about a path to the predetermined logical unit from the higher-level apparatus.

Abstract: Recommending changes to a storage system, including: identifying, using predicted characteristics of one or more workloads executing on the storage system, one or more configuration changes to the storage system that would improve the operation of the storage system; selecting, from the one or more configuration changes to the storage system that would improve the operation of the storage system, a preferred configuration change; and recommending the preferred configuration change.

Abstract: Packet routing between memory devices and related apparatuses, methods, and memory systems are disclosed. An apparatus of a memory device includes a memory controller, two or more memory interfaces, packet relay logic configured to control the two or more memory interfaces, and a switch. The switch is configured to pass a received packet received through a first memory interface of the two or more memory interfaces to the memory controller responsive to a determination that the received packet indicates the memory device as a destination of the received packet. The switch is also configured to pass the received packet through a second memory interface of the two or more memory interfaces toward an other memory device responsive to a determination that the received packet indicates the other memory device as the destination of the received packet.

Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive in a storage system, from a host device, mapping information associating a key identifier of a datastore-level key with a corresponding datastore comprising multiple logical storage devices of the storage system, to store the mapping information in a datastore-level key data structure of the storage system, to utilize the key identifier to obtain in the storage system the datastore-level key from a key management server external to the storage system, and responsive to receipt of at least one IO operation from the host device relating to at least one of reading or writing encrypted data of at least one of the logical storage devices of the datastore, to utilize the obtained datastore-level key to access the encrypted data in unencrypted form in the storage system.

Abstract: A data management method is applied to a computing system. The computing system includes a plurality of NUMA nodes, each NUMA node includes a processor and a memory, and each memory is used to store a data block. In the method, a processor in a NUMA node receives an operation request for a data block, and the processor processes the data block, and allocates a replacement priority of the data block in cache space of the NUMA node based on an access attribute of the data block, where the access attribute of the data block includes a distance between a home NUMA node of the data block and the NUMA node.

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

Abstract: A storage device includes non-volatile memory, a storage controller including a first controller processor connected to the non-volatile memory, and a second controller processor connected to the non-volatile memory, and shared memory to store a mapping table. The shared memory may be connected to the first controller processor and the second controller processor to share mapping table information between the first controller processor and the second controller processor. The storage controller may set a power mode of the first controller processor and the second controller processor based on an input/output intensity.

Abstract: A reconfigurable server includes improved bandwidth connection to adjacent servers and allows for improved access to near-memory storage and for an improved ability to provision resources for an adjacent server. The server includes processor array and a near-memory accelerator module that includes near-memory and the near-memory accelerator module helps provide sufficient bandwidth between the processor array and near-memory. A hardware plane module can be used to provide additional bandwidth and interconnectivity between adjacent servers and/or adjacent switches.

Abstract: A downloaded app controls a device to recognize whether a connected card reader is an unsupported card reader or whether an unsupported card is supplied to the connected card reader. The app automatically generates support for the unsupported card reader or unsupported card by reading the identifying information from the unsupported card reader or unsupported card, modifying an existing driver support file by adding the identifying information to the existing driver support file to create a modified driver support file, and testing the unsupported card reader or unsupported card using the modified driver support file. If the tests are successful, the app then supplies the modified driver support file to other devices separate from the printer.

Abstract: A data storage system configured to optimize selection of a plurality of data storage devices. The system includes a processor and a computer readable medium operably coupled thereto, the computer readable medium including a plurality of instructions stored in association therewith that are accessible to, and executable by, the processor, to perform storage device selection operations which include detecting and gathering storage device information for storing data recordings to the plurality of data storage devices, determining, by a storage load balancer, a plurality of storage efficiency scores for the plurality of data storage devices using a loss function and the gathered storage device information, generating a storage efficiency table, and assigning, by the storage load balancer, a first data recording to one of the plurality of data storage devices based on the storage efficiency table and an efficiency score threshold for the plurality of storage efficiency scores.

Abstract: Disclosed is a method for data processing applied to a solid state drive, a computer device and a computer-readable storage medium. The method includes acquiring an interface protocol command received by the solid state drive. The method also includes parsing the interface protocol command to obtain I/O information from the interface protocol command. The I/O information includes at least an I/O timestamp, an I/O type, and an I/O size. The method further includes invoking machine learning based on the I/O information to predict I/O information of a first future time period, so that a processor of the solid state drive is configured to proactively execute management functions according to the prediction results.

Abstract: Methods, apparatus, and processor-readable storage media are provided herein for storage volume creation using performance volumes and capacity volumes. An example computer-implemented method includes configuring a storage system with at least first and second storage tiers each comprising a plurality of storage devices; creating a virtual storage volume having a first portion corresponding to at least a portion of the plurality of storage devices of the first storage tier and a second portion corresponding to at least a portion of the plurality of storage devices of the second storage tier; and processing input-output requests from one or more host devices associated with the virtual storage volume, wherein the processing comprises moving data between the first portion and the second portion of the virtual storage volume so that each of the input-output requests is processed using the first portion of the virtual storage volume.

Abstract: An apparatus including a plurality of page circuits and a common request circuit. The page circuits may each be implemented within a respective memory bank controller of a memory bank set and store an address and determine a page hit status. The common request circuit may be implemented within the memory bank set and store client requests and issue a command corresponding to the client requests in response to the page hit status and an order of storage of the client requests. The page circuits may comprise half a storage depth of the common request circuit. The common request circuit may be shared between each of the memory bank controllers of the memory bank set. The memory bank controllers may control access to a random access memory. The address, the client requests and the page hit status may enable buffering to provide a preview of upcoming client requests.

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

Abstract: A data processing system may include a plurality of memory modules, a controller, a power supply and a plurality of switches. Each of the memory modules may include a plurality of pages. The controller may control operations of the memory modules. The power supply may provide the memory modules with a power. The switches may be arranged corresponding to each of the memory modules. The switches may be selectively driven in response to a switch drive signal from the controller.

Abstract: A processing unit such as a graphics processing unit (GPU) includes a plurality of vector signal processors (VSPs) that include multiply/accumulate elements. The processing unit also includes a plurality of registers associated with the plurality of VSPs. First portions of first and second matrices are fetched into the plurality of registers prior to a first round that includes a plurality of iterations. The multiply/accumulate elements perform matrix multiplication and accumulation on different combinations of subsets of the first portions of the first and second matrices in the plurality of iterations prior to fetching second portions of the first and second matrices into the plurality of registers for a second round. The accumulated results of multiplying the first portions of the first and second matrices are written into an output buffer in response to completing the plurality of iterations.

Abstract: An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality of cores; and an interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores.

Abstract: A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.

Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.

Abstract: This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.