Patents Examined by Errol Fernandes
  • Patent number: 10249568
    Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 10236357
    Abstract: A semiconductor device having stable electrical characteristics is provided. A semiconductor device that can be miniaturized or highly integrated is provided. One embodiment of the present invention includes a transistor including an oxide, a first barrier layer over the transistor, and a second barrier layer in contact with the first barrier layer. The oxide is in contact with an insulator including an excess-oxygen region. The insulator is in contact with the first barrier layer. The first barrier layer has a thickness greater than or equal to 0.5 nm and less than or equal to 1.5 nm. The second barrier layer is thicker than the first barrier layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasumasa Yamane, Ryo Tokumaru, Hiromi Sawai
  • Patent number: 10229940
    Abstract: The present invention provides a manufacturing technique of a semiconductor device and a display device using a peeling process, in which a transfer process can be conducted with a good state in which a shape and property of an element before peeling are kept. Further, the present invention provides a manufacturing technique of more highly reliable semiconductor devices and display devices with high yield without complicating the apparatus and the process for manufacturing. According to the present invention, an organic compound layer including a photocatalyst substance is formed over a first substrate having a light-transmitting property, an element layer is formed over the organic compound layer including a photocatalyst substance, the organic compound layer including a photocatalyst substance is irradiated with light which has passed through the first substrate, and the element layer is peeled from the first substrate.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Masafumi Morisue, Hajime Kimura, Shunpei Yamazaki
  • Patent number: 10224281
    Abstract: A semiconductor structure is provided that includes a first interconnect dielectric layer containing a first interconnect metal structure embedded therein. A second interconnect dielectric layer containing a second interconnect metal structure embedded therein is located atop the first interconnect dielectric layer. A metallic blocking layer is present that separates a surface of the second interconnect metal structure from a surface of the first interconnect metal structure. The metallic blocking layer has a lower resistivity than the first and second interconnect metal structures. The metallic blocking layer prevents electromigration of metallic ions from the first and second interconnect metal structure.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10224976
    Abstract: An apparatus of a mobile communication device comprises at least one radio with signal processing circuitry arranged to transmit and receive radio frequency (RF) signals. The apparatus includes a plurality of display components. An antenna layer is coupled to the signal processing circuitry and is configured for transmission and reception of the RF signals. The antenna layer is disposed between one of the plurality of display panel components and at least one isolation layer. The plurality of display panel components includes at least one of a protection coating layer, a display panel, a touch panel, or a cover.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Mei Chai, Helen Kankan Pan, Bryce Horine, Harry G. Skinner
  • Patent number: 10217637
    Abstract: Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Qianwen Chen, Bing Dang, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker
  • Patent number: 10217887
    Abstract: The crystalline silicon-based solar cell includes a first intrinsic silicon-based thin-film, a p-type silicon-based thin-film, a first transparent electrode layer, and a patterned collecting electrode on a first principal surface of an n-type crystalline silicon substrate; and a second intrinsic silicon-based thin-film, an n-type silicon-based thin-film, a second transparent electrode layer, and a plated metal electrode on a second principal surface of the n-type crystalline-silicon substrate. On a peripheral edge of the first principal surface, an insulating region freed of a short-circuit between the first transparent electrode layer and the second transparent electrode layer is provided. The plated metal electrode is formed on an entire region of the second transparent electrode layer.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 26, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Toshihiko Uto, Daisuke Adachi, Hisashi Uzu
  • Patent number: 10211255
    Abstract: Disclosed examples provide wafer-level integration of magnetoresistive sensors and Hall-effect sensors in a single integrated circuit, in which one or more vertical and/or horizontal Hall sensors are formed on or in a substrate along with transistors and other circuitry, and a magnetoresistive sensor circuit is formed in the IC metallization structure.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: February 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dok Won Lee, William David French, Keith Ryan Green
  • Patent number: 10205131
    Abstract: The disclosure provides a mask plate assembly, a method for fabricating an electroluminescent layer, a display panel and a method for driving the same. The mask plate assembly includes a first color mask plate, a second color mask plate, and a third color mask plate each having a plurality of rectangular openings. First openings of the first color mask plate and second openings of the second color mask plate are of a length in a row direction, which is substantially twice as that of third openings of the third color mask plate in the row direction. When the respective mask plates are aligned with one another, the first openings, the second openings, and the third openings are arranged alternately in an order of a first opening, a third opening, a second opening, and another third opening.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Haidong Wu, Weilin Lai, Juanjuan Bai
  • Patent number: 10199366
    Abstract: A method of manufacturing a semiconductor package, the method including forming a hole that penetrates an interconnect substrate; providing a first carrier substrate below the interconnect substrate; providing a semiconductor chip in the hole; forming a molding layer by coating a molding composition on the semiconductor chip and the interconnect substrate; adhering a second carrier substrate onto the molding layer with an adhesive layer; removing the first carrier substrate to expose a bottom surface of the semiconductor chip and a bottom surface of the interconnect substrate; forming a redistribution substrate below the semiconductor chip and the interconnect substrate; detaching the second carrier substrate from the adhesive layer; and removing the adhesive layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungwon Kim, Su-Jin Kwon, Junwon Han, Hyunwoo Kim, Byung Lyul Park
  • Patent number: 10199509
    Abstract: A high-performance semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a first metal oxide covering at least part of the first transistor, an insulating film over the first transistor and the second transistor, and a second metal oxide over the insulating film. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide, a first source electrode, a first drain electrode, a second gate insulating film, and a second gate electrode. The second transistor includes a third gate electrode, a third gate insulating film, a second oxide, a second source electrode, a second drain electrode, a fourth gate insulating film, and a fourth gate electrode. The first gate insulating film and the second gate insulating film are in contact with the first metal oxide.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: February 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuta Endo
  • Patent number: 10199404
    Abstract: An array substrate, a manufacturing method thereof and a display device are provided by the present disclosure. The manufacturing method includes: providing a base substrate; forming a plurality of pixel electrodes on the base substrate, in which the operation of forming the plurality of pixel electrodes includes: depositing a first transparent conductive film, and forming the plurality of pixel electrodes and a connection unit for connecting adjacent pixel electrodes by patterning the first transparent conductive film; forming a passivation layer on the plurality of pixel electrodes, and patterning the passivation layer to expose at least a portion of the connection unit; and processing the exposed portion of the connection unit, so that the plurality of interconnected pixel electrodes are electrically insulated.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 5, 2019
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xiuxing Fu, Zhen Wei, Feng Li
  • Patent number: 10192850
    Abstract: First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: January 29, 2019
    Assignee: SiTime Corporation
    Inventors: Paul M. Hagelin, Charles I. Grosjean
  • Patent number: 10177234
    Abstract: A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 8, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nariaki Tanaka, Tohru Oka
  • Patent number: 10177347
    Abstract: In a substrate bonding step of bonding an element original substrate to a counter original substrate through an intermediate layer so that a thin film element layer and a terminal group formed in the element original substrate face a second resin substrate layer formed in the counter original substrate, to manufacture a substrate bonded body, a terminal portion sealing member is formed in a frame shape surrounding the terminal group between the element original substrate and the counter original substrate.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 8, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yuki Yasuda, Tetsunori Tanaka
  • Patent number: 10170377
    Abstract: A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a plurality of gate structures, a spacer formed adjacent each of the plurality of gate structures, and conductive source/drain contact structures positioned adjacent each of the plurality of gate structures and separated from the associated gate structure by the spacer. A first portion of the conductive source/drain contact structures of a subset of the plurality of gate structures is recessed at a first axial position along a selected gate structure of the plurality of gate structures to define a cavity. A selected source/drain contact structure is not recessed. A first dielectric layer is formed in the cavity. A conductive line contacting the selected source/drain contact structure in the first axial position is formed.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Min-Hwa Chi
  • Patent number: 10163714
    Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 25, 2018
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Nadine Collaert
  • Patent number: 10163964
    Abstract: The present technology relates to a solid-state imaging element, an imaging device, and an electronic device that can improve transfer efficiency of a charge accumulation unit (MEM) and can increase the number of saturation electrons Qs. In a case where a charge voltage conversion unit (FD) is connected to a center of a charge accumulation unit (MEM) in each pixel and pixels are arrayed in an array, a column in which photoelectric conversion units (PD) are arrayed and a column including charge voltage conversion units (FD) and pixel transistors are arrayed in parallel. The present technology can be applied to a CMOS image sensor.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: December 25, 2018
    Assignee: SONY CORPORATION
    Inventor: Ryoto Yoshita
  • Patent number: 10163910
    Abstract: Described herein is a technique capable of suppressing the deviation in the characteristic of the semiconductor device. A method of manufacturing a semiconductor device may include: (a) receiving a data obtained by measuring a width of a first pillar between first grooves in a center region of a substrate and a width of a second pillar between second grooves in a peripheral region of the substrate; and (b) forming a width adjusting film on surfaces of the first grooves and the second grooves such that a sum of the width of the first pillar and a thickness of a first portion of the width adjusting film in the center region and a sum of the width of the second pillar and a thickness of a second portion of the width adjusting film in the peripheral region are within a predetermined range.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: December 25, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Atsushi Moriya
  • Patent number: 10158042
    Abstract: A method of producing optoelectronic semiconductor components includes A) providing a semiconductor layer sequence on a carrier top of a carrier, B) patterning the semiconductor layer sequence such that at least one mesa structure is formed with side faces, C) applying at least a portion of a cladding to the semiconductor layer sequence with the mesa structure by a conformal coating method such that all free surfaces are covered by the cladding), and D) anisotropically etching the cladding such that a flank coating is created from the cladding, which coating is limited with a tolerance of at most 200% of a mean thickness of the flank coating to the side faces of the mesa structure and completely encloses the mesa structure, wherein step D) takes place without an additional etching mask for the anisotropic etching.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: December 18, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Korbinian Perlzmaier, Andreas Biebersdorf