Abstract: A pixel structure comprises an epitaxial layer (1) of a first conductivity type. A photo-sensitive element comprises a first region (4) of a second conductivity type and a second region (3) of the first conductivity type positioned between the epitaxial layer (1) and the first region (4). A charge storage node (ø2) is arranged to store charges acquired by the photo-sensitive element, or to form part of a charge storage element. A third region (2) of the second conductivity type is positioned between the charge storage node and the epitaxial layer. The pixel structure further comprises a charge-to-voltage conversion element (13) for converting charges from the charge storage node to a voltage signal and an output circuit (21, 22) for selectively outputting the voltage signal from the pixel structure.

Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.

Abstract: Disclosed examples provide wafer-level integration of magnetoresistive sensors and Hall-effect sensors in a single integrated circuit, in which one or more vertical and/or horizontal Hall sensors are formed on or in a substrate along with transistors and other circuitry, and a magnetoresistive sensor circuit is formed in the IC metallization structure.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes forming an opening in the dielectric layer. A dielectric constant of a first portion of the dielectric layer is less than that of a second portion of the dielectric layer surrounding the opening. The method further includes forming a conductive feature in the opening. The second portion is between the first portion and the conductive feature. In addition, the method includes modifying an upper portion of the first portion to increase the dielectric constant of the upper portion of the first portion. The method also includes removing the upper portion of the first portion and the second portion.

Abstract: An electrical device comprising a ribbed molded body housing an electrical component is provided. The ribbed molded body includes at least one surface or portion having a plurality of ribs along at least a portion of the surface. The electrical component may be a passive or active electrical component. The electrical component may be connected to a lead frame and molded into the ribbed molded body.

Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.

Abstract: A semiconductor structure is provided that includes a first interconnect dielectric layer containing a first interconnect metal structure embedded therein. A second interconnect dielectric layer containing a second interconnect metal structure embedded therein is located atop the first interconnect dielectric layer. A metallic blocking layer is present that separates a surface of the second interconnect metal structure from a surface of the first interconnect metal structure. The metallic blocking layer has a lower resistivity than the first and second interconnect metal structures. The metallic blocking layer prevents electromigration of metallic ions from the first and second interconnect metal structure.

Abstract: The present disclosure relates to a method of forming a micro-electro mechanical system (MEMs) structure. In some embodiments, the method may be performed by providing a device substrate having a first MEMS device and a second MEMS device, and by providing a capping structure having a first cavity and a second cavity. The capping structure is bonded to the device substrate, such that the first cavity is arranged over the first MEMS device and the second cavity is arranged over the second MEMS device. A first pressure is established within the first cavity and the second cavity. A vent is selectively etched within the capping structure to change the first pressure within the second cavity to a second pressure, which is different from the first pressure.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a System on Chip (SoC) die; an integrated passive device (IPD); and a first switch, coupled between the SoC die and the IPD; wherein the IPD and the SoC die are disposed in different wafers and bonded together, and the first switch is controlled to disconnect the IPD from the SoC die when the IPD is under a test; and the first switch is controlled to connect the IPD with the SoC die when the IPD is not under the test. A test system for testing an IPD of a semiconductor device and an associated method are also disclosed.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract: There is provided a method of forming an etching-purpose mask structure on an insulating film containing silicon and oxygen, which includes: forming an intermediate film containing silicon, carbon, nitrogen and hydrogen as main components by supplying a first process gas onto the insulating film formed on a substrate; and subsequently, forming a tungsten film by supplying a second process gas containing a compound of tungsten to the substrate to replace some of silicon constituting the intermediate film with tungsten.

Abstract: A semiconductor device includes a first gate stack and a second gate stack over a substrate, an isolation structure in the substrate, a first epitaxial (epi) material in the substrate between the first gate stack and the isolation structure, and a second epi material in the substrate between the first gate stack and the second gate stack. The first gate stack is between the isolation structure and the second gate stack. The first epi material includes a first upper surface having a first crystal plane. The second epi material includes a second upper surface having a second crystal plane and a third upper surface having a third crystal plane, and first crystal plane is different from both the second crystal plane and the third crystal plane.

Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.

Abstract: The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the underbump metal pad.

Abstract: A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer layer. An epitaxial deposition process is performed to form an in situ carbon-doped strain relaxed buffer layer in the trench. A channel semiconductor material is formed on the initial strain relaxed buffer layer and on the in situ carbon-doped strain relaxed buffer layer in the trench. A plurality of fin-formation trenches that extend into the initial strain relaxed buffer layer is formed so as to thereby form an NMOS fin including the channel semiconductor material and the in situ carbon-doped strain relaxed buffer layer and a PMOS fin including the channel semiconductor material and the initial strain relaxed buffer layer. A recessed layer of insulating material and gate structures are formed around the NMOS fin and the PMOS fin.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the P-well so as to extend under the pinning layer and the P?-type impurity region and be in contact with the P?-type impurity region and the gate insulating film, and an N+-type impurity region that is located in the P-well and includes a portion that is under a second end portion of the gate electrode.

Abstract: Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is in contact with the P?-type impurity region and the gate insulating film, and an N??-type impurity region that surrounds at least a portion of the N?-type impurity region in plan view.

Abstract: A preparation method of an oxide thin-film transistor is disclosed, and this method includes: forming a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode; forming of the active layer, the source electrode and the drain electrode includes: sequentially forming an oxide semiconductor thin film and a source-drain electrode metal thin film on a base substrate, an entire surface of the oxide semiconductor thin film being in direct contact with the source-drain electrode metal thin film; and patterning the oxide semiconductor thin film and the source-drain electrode metal thin film with a dual-tone mask so as to form the active layer, the source electrode and the drain electrode by a single patterning process.

Abstract: A communication device includes at least one radio that comprises signal processing circuitry, and at least one antenna coupled to the signal processing circuitry to send and receive radio signals. A component of the communication device requires user visibility and includes an isolator for isolating the at least one antenna, the isolator comprising at least one film that includes a transparent conductor. The component that requires user visibility may be a display screen or part of the chassis of a transparent communication device. The transparent conductor comprises a transparent conducting oxide such as indium tin oxide, indium tin oxide ink, graphite material, carbon nanotubes, or a conductive polymer.