Abstract: A display device is provided, which includes a substrate structure containing a substrate with a pixel region, and the pixel region includes an aperture region. A metal oxide semiconductor transistor is disposed over the substrate and includes a metal oxide semiconductor layer with a first channel region, a first gate electrode corresponding to the first channel region, and a silicon oxide insulating layer on the metal oxide semiconductor layer. The silicon oxide insulating layer includes an opening corresponding to the aperture region. A polysilicon transistor is disposed over the substrate. The display device also includes an opposite substrate structure, and a display medium between the substrate structure and the opposite substrate structure.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.

Abstract: It is an object of the invention to provide a light emitting device which can display a superior image in which luminescent color from each light emitting layer is beautifully displayed and power consumption is lowered in a light emitting element in which light emitting layers are stacked. One feature of the invention is that, in a light emitting element which comprises light emitting layers stacked between electrodes, each distance between each light emitting layer and an electrode is approximately oddly multiplied ¼ wavelength by controlling a thickness of a layer provided therebetween to enhance luminous output efficiency. Another feature of the invention is that a drive voltage is lowered using a high conductive material for the layer compared with a conventional element.

Abstract: A semiconductor device includes a first fin on a substrate, a gate electrode on the substrate to intersect the first fin, an epitaxial layer on both sides of the gate electrode to contact side surfaces of the first fin, and a metal alloy layer which contacts an upper surface of the first fin and part of the epitaxial layer, wherein a first region of the first fin has a higher doping concentration than a second region of the first fin which is located under the first region.

Abstract: A semiconductor device includes a semiconductor substrate, a device layer located at an upper surface of the semiconductor substrate, an insulating layer located on the device layer, and a through electrode. The through electrode includes a body located in a through hole provided in the insulating layer and a head located on the body and the insulating layer and is electrically connected to an upper-layer wiring in the device layer. A perimeter of the head on a lower surface side thereof is smaller than a perimeter of the head on an upper surface side thereof.

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor element arranged on a predetermined surface side of the semiconductor substrate. The semiconductor element includes: a first region portion at which a first conductivity type semiconductor region is arranged on the surface side of the semiconductor substrate; a second region portion at a position separated from the first region portion; and a gate electrode arranged between the first region portion and the second region portion through an insulating film. In the first region portion, a first conductivity type semiconductor region is arranged. In the second region portion, a first conductivity type semiconductor region and a second conductivity type semiconductor region are alternately arranged.

Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate including a high-voltage well region. The device further includes a gate dielectric structure and a gate. The gate dielectric structure includes a first dielectric layer over the high-voltage well region and a second dielectric layer over the first dielectric layer. The second dielectric layer has a U-shaped or ring-shaped contour as viewed from a top-view aspect, so as to form an opening exposing the first dielectric layer. The gate is disposed over the second dielectric layer and extends onto the exposed first dielectric layer via the opening. The device further includes a drift doping region in the high-voltage well region and a source/drain doping region in the drift doping region. A method for fabricating the high-voltage semiconductor device is also provided.

Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.

Abstract: Provided herein is a resin structure having high heat dissipation, and desirable adhesion at the interface with a heat generating device. The resin structure is provided on a substrate to dissipates heat of the substrate to outside, and includes: a water-based coating material layer provided on the substrate and including a water-based coating material, and fillers having an average particle size of 30 ?m to 150 ?m; and a resin layer provided on the water-based coating material layer and containing a thermosetting resin. The fillers have a far-infrared emissivity of 0.8 or more, and an average aspect ratio of 1 to 12 as measured as a ratio of lengths along the long axis and the short axis through the center of gravity of the fillers. At least 80% of the total number of fillers has a length that is at least 1.

Abstract: An electronic device comprising a first substrate having a device area, a first sealing element comprising an anelastic material and a second sealing element being a metal. The first sealing means and the second sealing means are arranged such that the inner side or the outer side of the sealing is completely formed by the second sealing element providing hermiticity and the other side is substantially formed by the first sealing element providing a flexible sealing.

Abstract: A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

Abstract: A display device is provided including a first substrate provided with a pixel, the pixel being provided with a light emitting region of a light emitting device formed by stacking a first electrode, a light emitting layer and second electrode in this order, a first insulating layer having an opening exposing the first electrode at a position corresponding to the light emitting region and provided above the first electrode, a second insulating layer having a certain thickness provided over the first insulating layer and outer region of the opening, and a sealing film provided covering the light emitting device above the second electrode.

Abstract: In a semiconductor device including an oxide semiconductor film, defects in the oxide semiconductor film are reduced. In addition, the electrical characteristics of a semiconductor device including an oxide semiconductor film are improved. Furthermore, the reliability of a semiconductor device including an oxide semiconductor film is improved. A semiconductor device including an oxide semiconductor layer and a pair of electrodes in contact with the oxide semiconductor layer and containing copper, aluminum, gold, or silver is provided.

Abstract: Disclosed is an image sensor, which is characterized by increased strength of adhesion between a photoconductive layer and a substrate, and which includes a protective film formed on the surface of a substrate having a pad electrode, a buffer layer formed on the protective film and composed of a precious metal material or an oxide material, a photoconductive layer formed on the buffer layer, and an upper electrode formed on the photoconductive layer.

Abstract: Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.

Abstract: A silicon-based photoelectric multiplier comprises a plurality of cells and a number of read-out lines, and at least one of a number read-out pads or a ring-like line, wherein the plurality of cells may be divided into a number of segments, and each one of the read-out lines may be electrically connected with the cells of at least one segment.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.

Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.