Abstract: A power supply for high voltage, low current gas discharge tubes such as neon, argon, and mercury vapor. A free running, flyback oscillator, converts D.C. voltage energy into radio frequency energy by means of a compact, ferrite transformer and associated circuitry. The primary winding is tuned by a resonant capacitor and driven by a power transistor. A high voltage, centertapped winding of a ferrite transformer drives the gas tube load directly. A feedback winding arranged across the transistor base and emitter junction sustains oscillation and controls the drive level of the transistor by means of a regulating circuit which controls the amplitude of the current. Oscillator starting is achieved by means of an on-off switch which supplies a single starting pulse to the power transistor or by means of a time delayed starting pulse.

Abstract: A memory device is presented having the option, using simple means, of using one basic chip for different pin-outs or chip configurations. The metal and pin-out option implementation are formed by: 1) a dual-function pad and associated circuitry with an option for either an Input/Output or an Input-only configuration and 2) rotation of the chip with respect to the orientation of the DIP (dual in-line package). The implementation of this invention has decreased area requirements and better performance capabilities than those of known prior-art implementations.

Abstract: A circuit and method for minimizing write recovery time in a Bi-CMOS SRAM by equalizing the bit-line voltages during a read access. A P-channel device whose drain, source and gate are connected to bit, bit-bar, and the write control signal, respectively, indirectly equalizes the bit-lines by equalizing the base voltages of the NPN bit-line load devices only when the column is selected for read access. This technique takes advantage of the current gain of the NPN transistor from the base to the emitter to provide fast bit-line equalization immediately following writes, thus minimizing the write recovery time.

Abstract: An associative memory comprises a CAM array which is divided into a plurality of blocks, block select means, decoder means, and output means. The associative memory receives an externally supplied input address having first, second, and third parts. Which entry row in the CAM should be compared with the first part (TAG address) of the input address is determined by the second and third parts of the input address. The block select means responsive to the second part of the input address selects a block in the CAM. The decoder means responsive to the third part of the input address selects one out of a plurality of entry rows in the selected block. A comparison operation is carried out in each of the entry rows in the selected block. Since not all the entry rows are selected for comparison operations, power consumption can be reduced.

Abstract: A multi-port memory device includes a row-column array, a random access port, a plurality of bidirectional serial access memory (SAM) ports, and a switching network. There is one SAM port for each of a plurality of sets of columns. The switching network selectively couples each SAM port with each set, each set with each other set, and each SAM port with each other SAM port. A video random access memory (VRAM) or a multi-port dynamic random access memory (DRAM) of the present invention provides increased flexibility in smaller die area.

Abstract: An electromagnetic radiation control device is proposed using visually transparent computers and associated components to control the device's optical memory and the characteristics of its active optical component all contained within a capsule. The invention can be applied to items such as eyeglasses, contact lenses, window panes, doors, building panels, mirrors, billboards, light shields, electronic displays (TV, etc), reducers, magnifiers, projection systems, sunlight reflectors, cameras and other lenses, portable transponders for the blind, optical prothesis, and any combination of the above.

Abstract: Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.

Abstract: The present invention relates to an output buffer for driving an output driver of a random access memory (RAM) circuit to either of opposite binary data values from a data source and a clock wherein the relative timing of data and clock signals is variable or uncertain, comprised of a source of data signals having pulses one of which has a rising edge either being earlier than a leading edge of a data pulse, being later than the leading edge of the data pul se, or being in a race condition with the data pulse, a source of data signals, a latency counter for receiving the clock signals and for outputting a latent control, apparatus for summing the latent clock signal and the data pulse, and apparatus for providing a signal to an output driver from the summing apparatus which is in sync with the latent clock signal.

Abstract: A dual transparent latch circuit is disclosed comprising two latches cross coupled together by two control lines to enable the latches collectively to input and output data at twice the frequency of the master clock frequency which controls the timing of each latch individually. The control lines are controlled by a clock generator such that one latch is enabled to receive and store data while the other latch is enabled to output data stored therein. At the same time, the latch receiving and storing the data is disabled from providing an output of the stored data and the latch providing the output is disabled from receiving and storing the data. The clock generator switches the states of the control lines such that they enable or disable the input of data to and output of data from the latches on each phase of the master clock signal. A dual transparent latch with triple edge timing is also disclosed.

Abstract: A semiconductor memory has sense amplifiers which are supplied with a first potential from a first supply line and a second potential from a second supply line. A switching element on the first supply line is controlled by the potential of the second supply line, its conductivity increasing as the potential of the second supply line moves toward the second potential. A similar switching element, controlled by the potential of the first supply line, can be provided on the second supply line.

Abstract: An information processing apparatus includes first, second and third upper electrodes provided on a first substrate, and first, second and third lower electrodes provided on a second substrate opposed to the first, second and third upper electrodes, respectively. Also provided are first, second and third detectors for detecting a first capacitance between the first upper and lower electrodes, a second capacitance between the second upper and lower electrodes and a third capacitance between the third upper and lower electrodes.

Abstract: An orthogonal coaxial-line-to-microstripline transition is described. The transition employs capacitively loaded troughline transmission line to interface between the coaxial line and the microstripline. Because the field configuration of the troughline shows similarities to both the coaxial line and the microstripline configurations, a well matched transition between coaxial line onto microstripline. The center conductor of the troughline can be bent at right angles with no mismatch. Dielectrically loading the troughline prevents higher order modes from radiating out of the trough.

Abstract: The present invention relates to a method of writing or reading a semiconductor random access memory (DRAM or SRAM) having plural sense amplifiers connected to lines and having data bus read and write amplifiers, comprised of providing a pair of data buses for access by each sense amplifier and each read and write amplifier, reading or writing one data bus while precharging the other data bus during a first read or write cycle, and reading or writing the other data bus while precharging the first data bus in a second read or write cycle following the first read or write cycle.

Abstract: A Newtonian binocular telescope (20), which is readily adaptable to popular telescope mounts, such as the Dobsonian mount (76), and which includes two primary mirrors (42a, 42b), and two secondary mirrors (32a, 32b), in a single tube (21) of either solid wall or open frame construction. The single tube (21) allows central secondary optical axes (34a, 34b) to be disposed in laterally and longitudinally separate parallel relation to one another so as to form a comfortable interocular axis (36) between them. Both telescopes' oculars (50a, 50b) are conveniently disposed adjacent an ocular wall (22) on a side of tube (21) nearest one of the telescopes. The viewer is provided easy access (91a, 91b and 92a, 92b) to primary alignment means (87a, 87b), which may be used to merge images between telescopes.

Abstract: A high capacity (1 Gbyte), high throughput (1.1 Gbyte/s) motionless-head parallel-readout optical disk, and a detector array integrated on substrate with an Si/PLZT Exclusive-NOR gate array, implement a fast retrieval (25 ms) associative memory/content addressable memory capable of 10.sup.10 bit-operations per second. The disk stores arrayed 1-D holograms, preferably computer-generated from 128.times.128 pixel images by Fourier transform. Reverse transform upon disk readout is by lenses, preferably by a single hybrid refractive/diffractive lens. The reconstituted 2-D image, or optical word, is detected and compared to an electrical data word in an fast integrated optoelectronic circuit. The circuit permits (i) a variably preset "match" detection threshold, and (ii) dynamically variable, sub-image, field size of the search. In a first mode of operation all images (or sub-images) that are sufficiently close to a preset query threshold are retrieved in one disk rotation.

Abstract: A heater assembly for microscope objectives is disclosed. The assembly includes a loop-shaped flexible heating element sized and constructed to surround and operatively engage microscope objectives of different sizes. The heating element is fixed to a rigid housing. A thermistor is fixed in one end section of a slidable, tubular member arranged with the housing to translate towards and away and into and out of engagement of the thermistor with microscope objectives. Electrical conducting wiring connects the heating element and thermistor with a controllable heat energy for regulating the heat energy source to the microscope objective. The housing also supports a lock screw for securing the tubular member with the housing.

Abstract: An oscillator (108) for a standby charge pump (102,104)in a dynamic random access memory part (30) includes a fuse (136). The fuse can be blown after testing the part while selecting redundant memory cells to reduce the frequency of the oscillator and obtain a lower power part. The oscillator (108) also drives the on-chip self-refresh circuits (106) that operate slower in response to the reduced frequency. Selecting redundant circuits also includes eliminating memory cells that pass the pause test, but by only a certain margin. Reducing the frequency of the oscillator driving the self-refresh circuits would otherwise cause failure of the cells that pass the pause test by only the certain margin. The oscillator circuit includes a ring of inverter stages (112) and a fused voltage bias circuit (110) generating one or another set of bias voltages (118,120) to the ring oscillator to alter its frequency of oscillation.

Abstract: The present invention provides method for erasing a flash memory wherein "overerasing" can be prevented. To erase the cell, a gate voltage of 3 volts is applied to a control gate electrode and a voltage of 15 volts is applied to a source. A drain is left floating. At that time, the accumulated electrons begin to be injected from the floating gate to the source by tunneling. The threshold voltage of the flash memory cell decreases into less than 3 volts in the erasing operation, the potential difference between the floating gate and the source decreases. This enables the amount of charge by F-N tunneling to decrease and the erasing speed to decrease accordingly.

Abstract: A front to back coefficient of thermal expansion difference between surfaces of a mirror segment is reduced by coating a selected surface. The other surface may be also coated in order to obtain an overall bulk coefficient of thermal expansion for the mirror segment. A plurality of mirror segments having coefficients of thermal expansion matched by coatings are selected for assembly thereby avoiding the need to physically change the positions of the various segments in order to bring them into correct relationship or to refocus the image using other optics.

Abstract: The circuit structure comprises a series of storage units, a data bus, an address bus, a line for a reading/writing signal, a precharge logic suitable for precharging the address bus with a precharge address and a precharge sensor suitable for enabling the operation of address decoders of the storage units with a given delay with respect to the end of the precharge. The structure also comprises a flip-flop for controlling the address buses and the precharge logic as well as a delay circuit capable of producing a stop-writing signal with a delay calculated on the basis of the time necessary for the writing of a datum in a storage register of the storage units.