Patents Examined by Eugene R. LaRoche
  • Patent number: 5406511
    Abstract: Memory cells are formed at mutually facing areas of conductive layers arranged in parallel in a lateral direction and conductive layers arranged in a direction orthogonal to the lateral direction. A plurality of capacitors are formed, as a matrix array, at those mutually facing area of the conductive layers crossing relative to each other in the mutually orthogonal relation. Each capacitor constitutes a memory cell. A plurality of capacity levels, each, are set as a corresponding capacitor level by varying a mutually facing area between the conductive layers.
    Type: Grant
    Filed: August 10, 1993
    Date of Patent: April 11, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Nogami
  • Patent number: 5406064
    Abstract: An IC card which operates at either an operation mode or a power save mode, the processing in the operation mode being carried but in accordance with a command signal inputted from a predetermined external equipment, and the power save mode being capable of terminating its operations and returning to the operation mode upon reception of a predetermined release signal, the IC card including an information processing circuit provided in the IC card and a release signal generating circuit for outputting, the release signal to the information processing circuit within the IC circuit at the time when the command signal from the external equipment is received, wherein the information processing circuit executes the process corresponding to the command signal received from the external equipment during the operation mode, and thereafter causes the IC card to move to the power save mode.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: April 11, 1995
    Assignee: Hitachi Maxell, Ltd.
    Inventor: Takehiro Takahashi
  • Patent number: 5406148
    Abstract: A data reading circuit comprising a first data line to which a first current signal having a first current value is supplied, a second data line to which a second current signal having a second current value is supplied, a current-voltage converter circuit connected between the first and second nodes for applying a first voltage potential difference, which corresponds to the difference between the first and second current values, between the first and the second nodes, a first node, a second node, a level shifting circuit connected between the first and second nodes and the third and fourth nodes for applying a second voltage potential difference, which is substantially equal to the first voltage potential difference in response to the same, between the third and fourth nodes and a feedback circuit connected between the first and second nodes and the third and fourth nodes for applying a third voltage potential difference, which is larger than the first voltage potential difference, between the first and seco
    Type: Grant
    Filed: January 13, 1994
    Date of Patent: April 11, 1995
    Assignee: Oki Electric Industry Co. Ltd.
    Inventor: Koichi Yokomizo
  • Patent number: 5406523
    Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating draft tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: April 11, 1995
    Assignee: Mosaid Technologies Incorporated
    Inventors: Richard C. Foss, Peter B. Gillingham, Robert F. Harland, Valerie L. Lines
  • Patent number: 5406508
    Abstract: In a content addressable memory, a plurality of non-volatile memory cells each are provided in conjunction with the associated one of a plurality of match lines, thresholds of the plurality of non-volatile memory cells are selectively altered on the basis of a teacher-signal, and in read out of data, selected is a match line associated with a non-volatile memory cell having a maximum weight, if the match signal appears on a plurality of match lines, the thresholds of the non-volatile memory cells being treated as the weights, thereby reading out data which has been stored in the word memory involved in the maximum weight.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: April 11, 1995
    Assignee: Kawasaki Steel Corporation
    Inventor: Izumi Hayashibara
  • Patent number: 5406522
    Abstract: DRAM devices embodying the present invention have longer potential effective values of refresh interval. A self-refresh interval signal may be set in association with its refresh interval to minimize power consumption during the self-refresh operation mode. An inspection method may pick up DRAM devices with efficiency and without deterioration of yields. When self-refresh interval control signal SELFS assumes the logic level "H" to turn P channel type MOS transistor Qp off and N channel type MOS transistor Qn on, the node N14 is brought to ground voltage VSS. The P channel type MOS transistor Qp and the N channel type MOS transistor Qn determine the time constant at which oscillation is generated. The oscillation output is applied to memory cells of the DRAM devices to enable the self-refresh mode of operation.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: April 11, 1995
    Inventor: Hiroshige Hirano
  • Patent number: 5406518
    Abstract: The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus includes an input port for receiving the ordered sequence of input data and the variable-length delay-time. The apparatus further includes an integrated data storage, a random access memory (RAM) for storing the ordered sequence of input data according to a storage-order corresponding to the ordered sequence of the input data. The apparatus further includes a delay output port for accessing and outputting the delay output item in the storage means according to the variable-length delay-time and the storage-order such that the delay output item is delayed by the variable-length delay-time.
    Type: Grant
    Filed: February 8, 1994
    Date of Patent: April 11, 1995
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Yun Sun, Yung-Jung Jan, Ching-Hsiang Yang
  • Patent number: 5406543
    Abstract: An optical head for writing and/or reading information on and/or from an optical record medium such as a magneto-optical record medium including a semiconductor substrate, a semiconductor laser mounted on a surface of the semiconductor substrate for emitting a laser beam, an objective lens for projecting the laser beam onto the optical record medium as a fine spot, a plurality of photodetectors firmed in the surface of the semiconductor substrate, and an optical block arranged on said semiconductor substrate to form an integral unit together with said semiconductor substrate. The optical block includes a hologram for diffracting a return beam reflected by said magneto-optical record medium and a polarization beam splitting plane arranged in substantially parallel with an optical axis of a zero order beam emanating from the hologram for splitting a pupil of the hologram.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: April 11, 1995
    Assignee: Olympus Optical Co., Ltd.
    Inventors: Shohei Kobayashi, Takeshi Yamazaki, Masato Miyata
  • Patent number: 5406509
    Abstract: The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized by: (1) a large dynamic range of electrical resistance values; and (2) the ability to be set at one of a plurality of resistance values within said dynamic range in response to selected electrical input signals so as to provide said single cell with multibit storage capabilities. The memory element also includes a pair of spacedly disposed contacts for supplying the electrical input signal to set the memory material to a selected resistance value within the dynamic range. At least a filamentary portion of the single cell memory element being setable, by the selected electrical signal to any resistance value in said dynamic range, regardless of the previous resistance value of said material.
    Type: Grant
    Filed: April 12, 1993
    Date of Patent: April 11, 1995
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Stanford R. Ovshinsky, Qiuyi Ye, David A. Strand, Wolodymyr Czubatyj
  • Patent number: 5406513
    Abstract: A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present invention can be utilized with N-Well, P-Well and dual Well processes. For example, the circuit is described relative to an N-Well process. An N-Well is formed in a p-type substrate. A network of p-channel transistors are formed in the N-Well and a network of n-channel transistors are formed in the p-type substrate. A continuous P+guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and the N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between the p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a parasitic SCR and also act as additional collectors of radiation induced current.
    Type: Grant
    Filed: February 5, 1993
    Date of Patent: April 11, 1995
    Assignee: The University of New Mexico
    Inventors: John Canaris, Sterling Whitaker, Kelly Cameron
  • Patent number: 5406546
    Abstract: In a magneto-optical disk comprising a disk-shaped substrate including a grooved region in its surface and a recording layer covering the grooved region, the groove is defined by a pair of opposed side walls and a bottom in a radial cross section of the substrate and has a depth from the substrate surface to the groove bottom. The angle .theta. included between tangents to the side walls is at least 120 degrees, and the groove has a half-value width of 0.90 to 1.15 .mu.m and a depth of 600 to 900 .ANG.. The disk produces satisfactory values of push-pull signal level, radial contrast, and C/N ratio.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: April 11, 1995
    Assignee: TDK Corporation
    Inventors: Kenji Uchiyama, Hirokazu Fujioka, Masanori Shibahara
  • Patent number: 5404325
    Abstract: An intermediate voltage generator incorporated in a dynamic random memory device is shared between digit lines and counter electrodes of storage capacitors forming parts of memory cells, and supplies an intermediate voltage through precharging transistors to digit lines already shifted to high low voltage levels and directly to the counter electrodes, wherein a switching transistor cuts off the voltage propagation path between the intermediate voltage generator and the precharging transistors in the precharging stage so that the storage capacitors are free from voltage fluctuation due to the precharging operation on the digit lines.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: April 4, 1995
    Assignee: NEC Corporation
    Inventor: Kazuo Shibata
  • Patent number: 5404328
    Abstract: A memory cell for storing data includes a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into the memory cell and outputting the data, and a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of the first field effect transistor, and a drain connected to the drain of the first field effect transistor. The second field effect transistor has a conduction type opposite to that of the first field effect transistor. The memory cell has a capacitor which has a first terminal receiving a select signal for identifying the memory cell, and a second terminal connected to the floating gates of the first and second field effect transistors. The data is stored in the floating gates of the first and second field effect transistors.
    Type: Grant
    Filed: June 20, 1994
    Date of Patent: April 4, 1995
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 5404326
    Abstract: A semiconductor memory apparatus comprises a flip-flop circuit formed of a pair of inverters formed of driver transistors formed on a semiconductor substrate and having an input and an output coupled to each other in a crossing fashion, and transistors formed on a semiconductor thin film formed on the semiconductor substrate, and a pair of access transistors coupled to drain electrodes of the inverters constructing the flip-flop circuit. In this semiconductor memory apparatus, a coupling capacitance is formed on an overlapping portion in which active layers of the semiconductor thin film transistors and gate electrodes of the semiconductor thin film transistors are overlapped to each other and a part of the overlapping portion in which the coupling capacitance is formed is formed within a contact hole, thereby forming a coupling capacitance between the gate electrode and the drain electrode of the inverters. A soft error, caused by an .alpha.
    Type: Grant
    Filed: June 28, 1993
    Date of Patent: April 4, 1995
    Assignee: Sony Corporation
    Inventor: Yutaka Okamoto
  • Patent number: 5404002
    Abstract: A backup method for a multiple source optical scanner which alerts an operator when one of the sources has failed. A controller monitors the operation of each source and flags the failed sources. In the case of a scanner having dual full-time channels, the controller removes power from the failed source and disregards the signal from the failed source. In the case of a scanner having non-simultaneously operating sources, the controller switches the remaining source of the scanner to full-time operation. If both sources have failed, power to the failed sources is turned off.
    Type: Grant
    Filed: May 17, 1993
    Date of Patent: April 4, 1995
    Assignee: AT&T Global Information Solutions Company
    Inventor: Hong Tang
  • Patent number: 5404330
    Abstract: A word line boosting circuit and a control circuit therefor in a semiconductor integrated circuit are included. A word line boosting control circuit is connected to receive block select information selecting a first or second memory cell array block synchronized to a predetermined row address, and selectively generates first and second word line voltages.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: April 4, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Taek Lee, Jong-Hyeon Choi
  • Patent number: 5404333
    Abstract: An amplifier is arranged with an actively clamped load. In a differential amplifier, a pair of emitter-coupled transistors has loads connected between the collectors and a voltage supply. Separate clamping transistors have their collector-emitter paths connected across respective ones of the loads. A clamping control circuit, responsive to an input signal, produces a variable control signal to clamp output signal swings across the loads. A similar clamping control circuit can be used with a single-ended amplifier. Such an amplifier having an actively clamped load is useful in sense amplifier circuit arrangements in semiconductor memory arrangements used in data processing systems.
    Type: Grant
    Filed: March 24, 1993
    Date of Patent: April 4, 1995
    Assignee: Texas Instruments, Inc.
    Inventor: Aswin N. Mehta
  • Patent number: 5404329
    Abstract: A boosting circuit is provided applicable in various semiconductor integrated circuits such as a word line boosting circuit in a semiconductor memory. Because a backgate electrode of a PMOS transistor connected between power supply potential and an output node is connected to the output node, the output node is precharged to the Vcc level during a boosting term. Therefore, the boosting condition by a MOS capacitor is alleviated in comparison with a conventional boosting circuit. Proper boosting operation can be carried out even at a lower level of a supplied power supply voltage. Therefore, operable margin of power supply voltage is enlarged.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: April 4, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadato Yamagata, Yoshikazu Morooka
  • Patent number: 5404331
    Abstract: Disclosed is an integrated circuit memory having a plurality of addressable elements and a plurality of redundant elements for substitution of the addressable elements. A configurable selection circuit for each redundant element allows for associating the redundant element with an address for access of the redundant element in place of an addressable element, upon permanent physical modification of the integrated circuit memory. Redundant element testing is provided by use of bypass circuitry, responsive to a redundant element test signal. The bypass circuitry includes circuitry associated with each redundant element, for simulating access of the redundant element without modification of the configurable selection circuit for the redundant element. Each redundant element has an address, unique among the redundant elements but duplicating an address for a regular element, which is used for accessing the redundant element during testing.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: April 4, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: David C. McClure
  • Patent number: 5404055
    Abstract: The disclosed structure and method route an input signal received at an input/output pin through multiple input/output cells to a routing resource. In one embodiment, each input/output cell can be programmed to provide either a combinatorial input signal or a registered input signal. Increased flexibility is achieved by routing the registered input signal or the combinatorial input signal of each cell to a routing resource via one or more I/O cells.
    Type: Grant
    Filed: September 1, 1993
    Date of Patent: April 4, 1995
    Assignee: Lattice Semiconductor Corporation
    Inventors: Kapil Shankar, Cyrus Y. Tsui