Abstract: A semiconductor device is provided, including a seal portion; an electronic element within the seal portion; first, second, and third lead terminals; first and second connecting elements; and first and second conductive bonding agents, one end of the first connecting element having a protrusion downward and electrically connected to a control electrode of the electronic element with the first conductive bonding agent, a first side surface extending from the one end to the other end of the first connecting element is parallel to an extending direction along which the one end of the second connecting element extends, a wall portion being disposed on a top surface of the one end of the second lead terminal, and the wall portion being in contact with the other end of the first connecting element.

Abstract: Systems, methods, and apparatuses are provided for self-aligned etch back for vertical three dimensional (3D) memory. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes removing portions of the semiconductor material to form first horizontal openings and depositing a fill in the first horizontal openings. The method can further include forming third vertical openings to expose third vertical sidewalls in the vertical stack and selectively removing the fill material to form a plurality of second horizontal openings in which to form horizontally oriented storage nodes.

Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

Abstract: A source electrode (5), a drain electrode (6) and a T-shaped gate electrode (9) are formed on a GaN-based semiconductor layer (3,4) to form a transistor. An insulating film (10,11) covering the T-shaped gate electrode (9) is formed. A property of the transistor is evaluated to obtain an evaluation result. A film type, a film thickness or a dielectric constant of the insulating film (10,11) is adjusted in accordance with the evaluation result to make a property of the transistor close to a target property.

Abstract: Methods and architectures for forming metal line plugs that define separations between two metal line ends, and for forming vias that interconnect the metal lines to an underlying contact. The line plugs are present in-plane with the metal lines while vias connecting the lines are in an underlying plane. One lithographic plate or reticle that prints lines at a given pitch (P) may be employed multiple times, for example each time with a pitch halving (P/2), or pitch quartering (P/4) patterning technique, to define both metal line ends and metal line vias. A one-dimensional (1D) grating mask may be employed in conjunction with cross-grating (orthogonal) masking structures that are likewise amenable to pitch splitting techniques.

Abstract: A semiconductor device includes a substrate, an active region, an isolation structure, a first metal line, gate structure, source/drain region, a source/drain contact, and a second metal line. The active region protrudes from a top surface of the substrate. The isolation structure is over the substrate and laterally surrounds the active region. The first metal line is in the isolation structure. The gate structure is over the active region. The source/drain region is in the active region. The source/drain contact is over the active region and is electrically connected to the source/drain region. The second metal line is over the gate structure and the source/drain contact, in which the second metal line vertically overlaps the first metal line.

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

Abstract: Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.

Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.

Abstract: A light-emitting device includes: a mounting substrate including a mounting surface; a light-emitting element disposed on the mounting surface; a light transmissive component disposed on the light-emitting element; and a resin component that covers a side surface of the light-emitting element and a side surface of the light transmissive component. The resin component includes a cover portion that covers an outer edge portion of a topmost surface of the light transmissive component. A height from the mounting surface to a top of the cover portion is greater than a height from the mounting surface to the topmost surface of the light transmissive component. The topmost surface of the light transmissive component includes an exposed region that is exposed from the resin component. The cover portion is disposed continuously along one side of the light transmissive component.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

Abstract: A method for generating a report regarding prioritizations of industrial automation devices in an industrial system may include determining a first score for each of the industrial automation devices. The first score represents a relative importance of each of the industrial automation devices. The method may also include determining a second score for each of one or more parts of each of the industrial automation devices. The second score represents a relative importance of each of the parts with respect to each other. The method may also include generating the report comprising the parts, the industrial automation devices, the first score for each of the industrial automation devices, the second score for each of the parts, or any combination thereof, wherein the report is organized according to the first score, the second score, or based on a combination of the first score and the second score.

Abstract: A connection structure: a first electronic component having a terminal pattern in which a plurality of terminals are arranged side by side in a radial form and a second electronic component having a terminal pattern corresponding to the terminal pattern of the first electronic component are anisotropically conductively connected using an anisotropic conductive film, (i) the effective connection area per terminal is 3000 ?m2 or more, and the number density of conductive particles in the anisotropic conductive film is 2000 particles/mm2 or more and 20000 particles/mm2 or less, (ii) as the anisotropic conductive film, adopted is an anisotropic conductive film in which the conductive particles are arranged in a lattice form, and the arrangement pitch and the arrangement direction are configured such that each terminal captures three or more conductive particles, or (iii) as the anisotropic conductive film, adopted is an anisotropic conductive film having a multiple circular region.

Abstract: A Schottky diode includes a cathode terminal in a high voltage region of a semiconductor die, an anode terminal in a low voltage region of the semiconductor die, where the anode terminal and the cathode terminal are separated by a junction isolation termination situated between the high voltage region and the low voltage region. The Schottky diode includes a junction barrier Schottky diode or a trench metal-oxide-semiconductor (MOS) Schottky diode. The junction isolation termination includes pzener rings. The semiconductor die includes a substrate of a first conductivity type, an epitaxial layer of a second conductivity type situated on the substrate, a well region of the second conductivity type situated in the epitaxial layer in the high voltage region, and coupled to the cathode terminal, a Schottky barrier situated on the epitaxial layer in the low voltage region, and coupled to the anode terminal.

Abstract: Disclosed is a photodetector which includes, in series along a stacking direction: a first layer forming a substrate of a first semiconductor material; a second layer forming a photoabsorbent layer of a second semiconductor material having a second gap; a third layer forming a barrier layer of a third semiconductor material; and a fourth layer forming a window layer of a fourth semiconductor material, the first material, the third material and the fourth material each having a gap larger than the second gap, the fourth material being n-doped or non-doped and the third material being non-doped or lightly p-doped when the second material is n-doped, and the fourth material being p-doped or non-doped and the third material being non-doped or lightly n-doped when the second material is p-doped.

Abstract: A method for adaptable machining includes (a) providing one or more images with a digital imaging system of each of a series of work pieces, (b) for each of the work pieces, selectively modifying a preprogrammed cutting tool path with regard to the image of the respective work piece, and (c) for each of the work pieces, performing a machining operation according to the respective selectively modified preprogrammed cutting tool path.

Abstract: In one general aspect, a device can include a leadframe including at least one of an external input terminal or an external output terminal, an interposer made of an insulating material, and a redistribution layer coupled to the interposer and made of a conductive material. The redistribution layer can include a plurality of traces. The device can also include a semiconductor die disposed between the redistribution layer and the leadframe.

Abstract: The invention relates to a process for manufacturing a heterojunction electronic component provided with an embedded barrier layer, the process comprising: depositing by epitaxy, in a vapour phase epitaxial growth chamber with an atmosphere exhibiting a first nonzero ammonia concentration, of a GaN precursor layer of the embedded barrier layer, comprising a first layer doped with a Mg or Fe dopant; placing, while maintaining the substrate in the chamber, the atmosphere at a second ammonia concentration at most equal to a third of the first concentration, in order to remove an upper part of the precursor layer; and then after the removal of the said upper part, while maintaining the substrate in the chamber, depositing by epitaxy of a layer of semiconductor material of the heterojunction electronic component to be manufactured, the said precursor layer then forming the embedded barrier layer under the said layer of semiconductor material.