Abstract: A first semiconductor package which is located on an upper side includes a first printed wiring board and an encapsulation resin for encapsulating a first semiconductor chip. A second semiconductor package which is located on a lower side includes a second printed wiring board. The first printed wiring board includes first lands and a first solder resist having first openings for exposing the first lands. The second printed wiring board includes second lands opposed to the first lands, respectively, and a second solder resist having second openings for exposing the second lands and opposed to the first openings, respectively. The first lands and the second lands are solder joined to each other through the first openings and the second openings, respectively. The opening area of the first opening is set to be smaller than the opening area of the second opening. This improves joint reliability.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates.

Abstract: Bulk finFET well contacts with fin pattern uniformity and methods of manufacture. The method includes providing a substrate with a first region and a second region, the first region comprising a well with a first conductivity. The method further includes forming contiguous fins over the first region and the second region. The method further includes forming an epitaxial layer on at least one portion of the fins in the first region and at least one portion of the fins in the second region. The method further includes doping the epitaxial layer in the first region with a first type dopant to provide the first conductivity. The method further includes doping the epitaxial layer in the second region with a second type dopant to provide a second conductivity.

Abstract: The present invention relates to light-emitting diodes. A light-emitting diode according to an exemplary embodiment of the present invention includes a first group including a plurality of first light emitting cells connected in parallel to each other, and a second group including a plurality of second light emitting cells connected in parallel to each other. Each first light emitting cell and second light emitting cell has a semiconductor stack that includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. At least two light emitting cells of the first light emitting cells share the first conductivity-type semiconductor layer, and at least two light emitting cells of the second light emitting cells share the first conductivity-type semiconductor layer.

Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a processing target film is formed above a substrate. A buffer layer in a polycrystalline state or an amorphous state is formed on the processing target film. A mask material is formed on the buffer layer. The processing target film is etched using the mask material as a mask. The buffer layer has an etching rate smaller than the processing target film.

Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.

Abstract: A method for fabricating a capacitor includes: (1) forming a bottom electrode on a substrate; (2) forming a template layer on the bottom electrode; (3) performing a plurality of atomic layer deposition (ALD) cycles by using water vapor as an oxidant thereby depositing a first TiO2 layer on the template layer; and (4) performing ozone pulse and purge step to transform entire thickness of the first TiO2 layer into rutile phase.

Abstract: An integrated circuit arrangement is provided, including a transistor including a gate region; and a wavelength conversion element, wherein the wavelength conversion element may include the same material or same materials as the gate region of the transistor.

Abstract: An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.

Abstract: A light emitting device having a light extraction structure, which is capable of achieving an enhancement in light extraction efficiency and reliability, and a method for manufacturing the same. The light emitting device includes a semiconductor layer having a multi-layered structure including a light emission layer; and a light extraction structure formed on the semiconductor layer in a pattern having unit structures. Further, the wall of each of the unit structures is sloped at an angle of ?45° to +45° from a virtual vertical line being parallel to a main light emitting direction of the light emitting device.

Abstract: Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies.

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Abstract: A lighting apparatus having wavelength-converting materials formed in a carrier layer is disclosed. In one embodiment, the lighting apparatus has a light source attached to a substrate that is assembled in a housing. The light source is configured to emit a substantially narrow band light that is transformed into broad-spectrum white light by the wavelength-converting materials positioned on the carrier layer. The wavelength-converting materials and the carrier layer are distanced away from the light source, such that the carrier layer is thermally isolated from the light source.

Abstract: An example turbine component cooling arrangement includes a film plate having a plurality of film channels extending from film channel entrances on a first side of the film plate to corresponding film channel exits on an opposing second side of the film plate. The arrangement also includes an impingement plate establishing a plurality of impingement channels. The impingement plate is spaced a distance from the film plate. The plurality of impingement channels are configured to direct a fluid across the distance to contact the film plate between adjacent ones of the film channel entrances. In one example, the distance from the film plate to the impingement plate is between two and four times more than diameter of one of the impingement channels.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Abstract: Disclosed is a light emitting device. The light emitting device includes a substrate including a plurality of lead electrodes; a mold member including a cavity on the substrate; a light emitting chip in the cavity and on at least one of the lead electrodes; a connecting member for electrically connecting at least one of the lead electrodes to the light emitting chip; a resin member in the cavity; a spacer part between the lead electrodes, the spacer part including a material different from materials of the mold member and the resin member; and an adhesive film between the mold member and the substrate.

Abstract: Signal processing solutions take advantage of microphones located on different devices and improve the quality of transmitted voice signals in a communication system. With usage of various devices such as Bluetooth headsets, wired headsets and the like in conjunction with mobile handsets, multiple microphones located on different devices are exploited for improving performance and/or voice quality in a communication system. Audio signals are recorded by microphones on different devices and processed to produce various benefits, such as improved voice quality, background noise reduction, voice activity detection and the like.