Patents Examined by Evan G Clinton
  • Patent number: 11329211
    Abstract: An active three-terminal superconducting device having an intersection region at which a hot spot may be controllably formed is described. The intersection region may exhibit current crowding in response to imbalances in current densities applied to channels connected to intersection region. The current crowding may form a hot spot, in which the superconducting device may exhibit a measurable resistance. In some cases, a three-terminal superconducting device may be configured to sense an amount of superconducting current flowing in a channel or loop without having to perturb the superconducting state or amount of current flowing in the channel. A three-terminal superconducting device may be used to read out a number of fluxons stored in a superconducting memory element.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: May 10, 2022
    Assignee: Massachusetts Institute of Technology
    Inventors: Adam N. McCaughan, Karl K. Berggren, Qingyuan Zhao
  • Patent number: 11325343
    Abstract: Ion-doped two-dimensional nanomaterials are made by inducing electronic carriers (electrons and holes) in a two-dimensional material using a captured ion layer at the surface of the material. The captured ion layer is stabilized using a capping layer. The induction of electronic carriers works in atomically-thin two-dimensional materials, where it induces high carrier density of at least 1014 carriers/cm2. A variety of novel ion-doped nanomaterials and p-n junction-based nanoelectronic devices are made possible by the method.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 10, 2022
    Assignee: Northeastern University
    Inventors: Swastik Kar, Ji Hao, Daniel Rubin, Yung Joon Jung
  • Patent number: 11322375
    Abstract: A silicon semiconductor wafer is transported into a chamber, and preheating of the semiconductor wafer is started in a nitrogen atmosphere by irradiation with light from halogen lamps. When the temperature of the semiconductor wafer reaches a predetermined switching temperature in the course of the preheating, oxygen gas is supplied into the chamber to change the atmosphere within the chamber from the nitrogen atmosphere to an oxygen atmosphere. Thereafter, a front surface of the semiconductor wafer is heated for an extremely short time period by flash irradiation. Oxidation is suppressed when the temperature of the semiconductor wafer is relatively low below the switching temperature, and is caused after the temperature of the semiconductor wafer becomes relatively high. As a result, a dense, thin oxide film having good properties with fewer defects at an interface with a silicon base layer is formed on the front surface of the semiconductor wafer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: May 3, 2022
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Akitsugu Ueda, Kazuhiko Fuse
  • Patent number: 11322384
    Abstract: According to one embodiment, a substrate processing apparatus and a substrate processing method that can improve the quality of substrates are provided.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 3, 2022
    Assignees: SHIN-ETSU ENGINEERING CO., LTD., SHIBAURA MECHATRONICS CORPORATION
    Inventors: Shunya Kubota, Emi Matsui, Katsuhiro Yamazaki, Yoshikazu Ohtani, Kyouhei Tomioka
  • Patent number: 11315879
    Abstract: A package substrate, including a substrate, a first structure disposed on the substrate and having a first through-portion, a first wiring layer disposed in the first through-portion on the substrate, a first insulating layer disposed in the first through-portion on the substrate and covering at least a portion of the first wiring layer, and a second wiring layer disposed on the first insulating layer, and a multi-chip package, including the package substrate, are provided.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yun Je Ji, Tae Seong Kim
  • Patent number: 11315859
    Abstract: A power module can include a casing mounted to a baseplate that contains a substrate with circuitry. The circuitry can include pins for coupling signals to/from the circuitry. These pins can extend through a cover portion of the casing so that an electronic substrate, such as a printed circuit board (PCB) can be press-fit onto the pins. When press-fit, the electronic substrate is supported and positioned by support pillars that extend from the base plate to above the cover portion of the casing. If the pins and the support pillars have different coefficients of thermal expansion, damage to connection points between the pins and the circuitry may occur. Here, a power module is disclosed that has thermally matched pins and support pillars so that when the system is thermally cycled over a range of temperatures, the connection points are not damaged by forces induced by thermal expansion.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: April 26, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Qing Yang, Yong Liu, Yushuang Yao
  • Patent number: 11315783
    Abstract: A method of fabricating a display substrate is provided. The method includes forming a conductive layer on a base substrate; and performing a chemical vapor deposition process to form an oxide layer on a side of an exposed surface of the conductive layer away from the base substrate, the exposed surface of the conductive layer including copper, the oxide layer formed to include an oxide of a target element M. The chemical vapor deposition process is performed using a mixture of a first reaction gas including oxygen and a second reaction gas including the target element M, at a reaction temperature in a range of 200 Celsius degrees to 280 Celsius degrees. A mole ratio of oxygen element to the target element M in the mixture of the first reaction gas and the second reaction gas is in a range of 40:1 to 60:1.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 26, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yuankui Ding, Heekyu Kim, Liangchen Yan, Ce Zhao, Bin Zhou, Yingbin Hu, Wei Song, Dongfang Wang
  • Patent number: 11309254
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11302820
    Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Blandine Duriez, Marcus Johannes Henricus Van Dal, Martin Christopher Holland, Gerben Doornbos, Georgios Vellianitis
  • Patent number: 11302842
    Abstract: A method for manufacturing a micro light emitting diode device is provided. A connection layer and a plurality of epitaxial structures are formed on a substrate, wherein the epitaxial structures are separated from each other and relative positions therebetween are fixed via the connection layer. A first pad is formed on each of the epitaxial structures. A plurality of light blocking layers are formed between the epitaxial structures, wherein the light blocking layers and the epitaxial structures are alternately arranged. Each of the epitaxial structures is bonded to a destination substrate after forming the light blocking layers. The substrate is removed to expose the connection layer. A light conversion layer is formed corresponding to each of the epitaxial structures, wherein a width of the light conversion layer is greater than or equal to a distance between any two of the light blocking layers.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: April 12, 2022
    Assignee: PlayNitride Inc.
    Inventors: Yu-Yun Lo, Chih-Ling Wu, Yi-Min Su, Yen-Yeh Chen, Yi-Chun Shih
  • Patent number: 11295957
    Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, a RDL structure, an underfill layer, a protection layer, and a cap. The TIV is aside the die. The encapsulant laterally encapsulates the die and the TIV. The RDL structure is electrically connected to the die. The underfill layer is disposed between the die and the RDL structure and laterally encapsulated by the encapsulant. The protection layer is overlying the die and the encapsulant. The cap covers a top surface of the TIV and laterally aside the protection layer. A top surface of the cap is higher than a top surface of the encapsulant and lower than a top surface of the protection layer.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
  • Patent number: 11289583
    Abstract: A method of forming a semiconductor device includes providing a substrate; forming mandrel patterns over the substrate; forming sacrificial patterns in openings between the mandrel patterns; removing the mandrel patterns; forming a dielectric layer in openings between the sacrificial patterns; removing the sacrificial patterns, resulting in a plurality of trenches; and forming a gate stack in each of the plurality of trenches.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Chi-On Chui, Kai-Hsuan Lee, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11282744
    Abstract: Device and method of forming the device are disclosed. A semiconductor device includes a back-end-of-line dielectric (BEOL) with a plurality of IMD levels over a substrate processed with front-end-of-line components. The BEOL includes an upper IMD level and upper metal lines, with a buffer layer over the upper metal lines. The buffer layer improves adhesion of the upper IMD layer which covers the upper metal lines. Improving the adhesion of the upper IMD layer improves the reliability of the device.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 22, 2022
    Assignee: Systems On Silicon Manufacturing Co. Pte. Ltd.
    Inventors: Pankaj Kumar Uttwani, Shankaran Chelliah, Yee Ming Chan
  • Patent number: 11276588
    Abstract: A method of processing a wafer includes a protective member affixing step of affixing a protective member whose area covers a face side or a reverse side of the wafer to the wafer, and after the protective member affixing step has been carried out, a ring-shaped stiffener removing step of removing a ring-shaped stiffener from the wafer. The ring-shaped stiffener removing step includes a ring-shaped stiffener separating step of dividing the wafer along an outer circumference of a device region to separate the device region and the ring-shaped stiffener from each other, and after the ring-shaped stiffener separating step has been carried out, a removing step of processing the ring-shaped stiffener with a grindstone to remove the ring-shaped stiffener from the wafer while a processing fluid is being supplied to the wafer.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: March 15, 2022
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 11251071
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Patent number: 11251093
    Abstract: An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: February 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Younsung Choi, Steven Lee Prins
  • Patent number: 11251142
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 11245050
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: February 8, 2022
    Assignee: Soitec
    Inventor: David Sotta
  • Patent number: 11217546
    Abstract: A method includes attaching a voltage regulator to a first redistribution structure of a first package. A second redistribution structure is formed over the voltage regulator, the voltage regulator being embedded in the second redistribution structure. The first substrate is attached to the second redistribution structure to form a second package including the first package. A first voltage may be provided to the second redistribution structure and through the second redistribution structure to the voltage regulator. The voltage regulator regulates the first voltage into a second voltage and provides the second voltage through the first redistribution structure to a first device die, where an output of the voltage regulator is attached directly to the first redistribution structure.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chien-Hsun Chen
  • Patent number: 11217479
    Abstract: A multiple metallization scheme in conductive features of a device uses ion implantation in a first metal layer to make a portion of the first metal layer soluble to a wet cleaning agent. The soluble portion may then be removed by a wet cleaning process and a subsequent second metal layer deposited over the first metal layer. An additional layer may be formed by a second ion implantation in the second metal layer may be used to make a controllable portion of the second metal layer soluble to a wet cleaning agent. The soluble portion of the second metal layer may be removed by a wet cleaning process. The process of depositing metal layers, implanting ions, and removing soluble portions, may be repeated until a desired number of metal layers are provided.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Ying Ho, Fang-I Chih, Hui-Chi Huang, Kei-Wei Chen