Patents Examined by Evan G Clinton
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Patent number: 11901248Abstract: Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core.Type: GrantFiled: March 27, 2020Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Robert L. Sankman, Rahul N. Manepalli, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Bharat P. Penmecha
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Patent number: 11901200Abstract: A silicon semiconductor wafer is transported into a chamber, and preheating of the semiconductor wafer is started in a nitrogen atmosphere by irradiation with light from halogen lamps. When the temperature of the semiconductor wafer reaches a predetermined switching temperature in the course of the preheating, oxygen gas is supplied into the chamber to change the atmosphere within the chamber from the nitrogen atmosphere to an oxygen atmosphere. Thereafter, a front surface of the semiconductor wafer is heated for an extremely short time period by flash irradiation. Oxidation is suppressed when the temperature of the semiconductor wafer is relatively low below the switching temperature, and is caused after the temperature of the semiconductor wafer becomes relatively high. As a result, a dense, thin oxide film having good properties with fewer defects at an interface with a silicon base layer is formed on the front surface of the semiconductor wafer.Type: GrantFiled: March 4, 2022Date of Patent: February 13, 2024Assignee: SCREEN Holdings Co., Ltd.Inventors: Akitsugu Ueda, Kazuhiko Fuse
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Patent number: 11894241Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.Type: GrantFiled: April 1, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mirng-Ji Lii, Chen-Shien Chen, Lung-Kai Mao, Ming-Da Cheng, Wen-Hsiung Lu
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Patent number: 11894292Abstract: A power module can include a casing mounted to a baseplate that contains a substrate with circuitry. The circuitry can include pins for coupling signals to/from the circuitry. These pins can extend through a cover portion of the casing so that an electronic substrate, such as a printed circuit board (PCB) can be press-fit onto the pins. When press-fit, the electronic substrate is supported and positioned by support pillars that extend from the base plate to above the cover portion of the casing. If the pins and the support pillars have different coefficients of thermal expansion, damage to connection points between the pins and the circuitry may occur. Here, a power module is disclosed that has thermally matched pins and support pillars so that when the system is thermally cycled over a range of temperatures, the connection points are not damaged by forces induced by thermal expansion.Type: GrantFiled: March 17, 2022Date of Patent: February 6, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Qing Yang, Yong Liu, Yushuang Yao
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Patent number: 11887917Abstract: A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.Type: GrantFiled: March 31, 2021Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Yang Liang Poh
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Patent number: 11887887Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: GrantFiled: June 27, 2022Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Patent number: 11887919Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.Type: GrantFiled: February 22, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yun Seok Choi
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Patent number: 11881466Abstract: A method for producing electronic devices includes fixing a die that includes an electronic component with integral contacts to a dielectric substrate. After fixing the die, a conductive trace is printed over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the substrate and the electronic component.Type: GrantFiled: April 26, 2018Date of Patent: January 23, 2024Assignee: ORBOTECH LTD.Inventors: Michael Zenou, Zvi Kotler, Ofer Fogel
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Patent number: 11876040Abstract: In one example, an electronic device, comprises a substrate, comprising a first dielectric having a top surface and a bottom surface, and a first conductor in the first dielectric and comprising a first via and a first trace over the first via. The first trace comprises a first trace sidewall and a first trace base, and the first via comprises a first via sidewall. The first conductor comprises a first arcuate vertex between the first trace sidewall and the first trace base, and a second arcuate vertex between the first via sidewall and the first trace base, an electronic component over the top surface of the substrate, and an encapsulant over the top surface of the substrate and contacting a lateral side of the electronic component. Other examples and related methods are also disclosed herein.Type: GrantFiled: May 25, 2021Date of Patent: January 16, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Sang Hyun Jin, Young Jin Kang, Jin Suk Jeong, Yun Kyung Jeong
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Patent number: 11876029Abstract: A method of manufacturing an electronic component module includes a sacrificial-body arrangement step of disposing a sacrificial body on a first principal surface of a support, the support including the first principal surface and a second principal surface, the sacrificial body being smaller than the first principal surface when viewed in a thickness direction of the support, a resin molding step of molding a resin structure on the first principal surface so as to cover the sacrificial body disposed on the first principal surface, a recess forming step of forming a recess in the resin structure by removing the sacrificial body, a wiring-layer forming step of forming a wiring layer on a side surface of the recess and on a principal surface of the resin structure, the principal surface connecting with the side surface, and a component mounting step of mounting an electronic component in the recess.Type: GrantFiled: August 6, 2021Date of Patent: January 16, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Takashi Iwamoto
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Patent number: 11862545Abstract: An integrated substrate, an electronic assembly, and manufacturing methods thereof are provided. The integrated substrate structure includes a coarse redistribution structure, fine redistribution segments, and conductive connectors. The coarse redistribution structure includes a coarse dielectric layer and a coarse circuitry embedded therein. The fine redistribution segments disposed over the coarse redistribution structure and disposed side by side and apart from one another. The respective fine redistribution segment includes a fine dielectric layer thinner than the coarse dielectric layer, and a fine circuitry embedded in the fine dielectric layer. The fine circuitry includes a dimension and a pitch finer than those of the coarse circuitry, and a layout density of the fine circuitry is denser than that of the coarse circuitry.Type: GrantFiled: June 24, 2021Date of Patent: January 2, 2024Inventor: Dyi-Chung Hu
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Patent number: 11862469Abstract: A method of forming a package structure includes the following steps. A first package structure is formed. The first package structure is connected to a second package structure. The method of forming the first package structure includes the following steps. A redistribution layer (RDL) structure is formed. A die is bonded to the RDL structure. The RDL structure is electrically connected to the die. A through via is formed on the RDL structure and laterally aside the die. An encapsulant is formed to laterally encapsulate the through via and the die. A protection layer is formed over the encapsulant and the die. A cap is formed on the through via and laterally aside the protection layer, wherein the cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the protection layer. The cap is removed from the first package structure.Type: GrantFiled: March 31, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
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Patent number: 11862624Abstract: An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate.Type: GrantFiled: May 20, 2021Date of Patent: January 2, 2024Inventors: Taemin Ok, Inmo Kim, Sujeong Kim, Daeseok Byeon
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Patent number: 11855004Abstract: A package structure is provided. The package structure includes a first conductive pad in an insulating layer, a first under bump metallurgy structure under the first insulating layer, and a first conductive via in the insulating layer. The first conductive via is vertically connected to the first conductive pad and the first under bump metallurgy structure. In a plan view, a first area of the first under bump metallurgy structure is confined within a second area of the first conductive pad.Type: GrantFiled: June 17, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Shu-Shen Yeh, Che-Chia Yang, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11855008Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.Type: GrantFiled: August 10, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
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Patent number: 11855043Abstract: A multi-chip module (MCM) includes a common substrate and first and second integrated circuit (IC) chips disposed on the common substrate. The first integrated circuit (IC) chip includes a first interface circuit disposed proximate a first edge of the first IC chip and a second interface circuit disposed proximate the first edge of the first IC chip. A first chiplet couples to the first interface circuit via a first link. A second chiplet couples to the second interface circuit via a second link. A first position of the first chiplet with respect to the first IC chip is staggered in a longitudinal dimension relative to a second position of the second chiplet with respect to the first IC chip.Type: GrantFiled: November 25, 2022Date of Patent: December 26, 2023Assignee: Eliyan CorporationInventors: Ramin Farjadrad, Syrus Ziai
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Patent number: 11854835Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.Type: GrantFiled: August 10, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mirng-Ji Lii, Chen-Shien Chen, Lung-Kai Mao, Ming-Da Cheng, Wen-Hsiung Lu
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Patent number: 11855037Abstract: The invention relates to a method (110) for producing an electrically conductive connection (112, 112?) on a substrate (114), comprising the following steps: a) providing a substrate (114), wherein the substrate (114) is configured for receiving an electrically conductive connection (112, 112?); b) providing a reservoir of an electrically conductive liquid alloy, wherein the reservoir has a surface at which the alloy has an insulating layer; c) providing a capillary (120) configured for taking up the electrically conductive liquid alloy; d) penetrating of a tip (122) of the capillary (120) under the surface of the reservoir and taking up of a portion of the alloy from the reservoir; and e) applying the portion of the alloy at least partly to the substrate (114) in such a manner that an electrically conductive connection (112, 112?) is formed from the alloy on the substrate (114), wherein the alloy remains on the substrate (114) by adhesion.Type: GrantFiled: August 22, 2019Date of Patent: December 26, 2023Assignee: Karlsruher Institut für TechnologieInventors: Uwe Bog, Michael Hirtz, Harald Fuchs, Jasmin Aghassi, Gabriel Cadilha Marques, Subho Dasgupta, Ben Breitung, Horst Hahn
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Patent number: 11848385Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.Type: GrantFiled: March 28, 2022Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Blandine Duriez, Marcus Johannes Henricus Van Dal, Martin Christopher Holland, Gerben Doornbos, Georgios Vellianitis
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Patent number: 11849597Abstract: A sensor includes an anode and a cathode, and a near-infrared photoelectric conversion layer between the anode and the cathode. The near-infrared photoelectric conversion layer is configured to absorb light of at least a portion of a near-infrared wavelength spectrum and convert the absorbed light into an electrical signal. The near-infrared photoelectric conversion layer includes a first material having a maximum absorption wavelength in the near-infrared wavelength spectrum and a second material forming a pn junction with the first material and having a wider energy bandgap than an energy bandgap of the first material. The first material is included in the near-infrared photoelectric conversion layer in a smaller amount than the second material.Type: GrantFiled: September 27, 2021Date of Patent: December 19, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Seok Leem, Rae Sung Kim, Hyesung Choi, Ohkyu Kwon, Changki Kim, Hwang Suk Kim, Bum Woo Park, Jae Jun Lee