Patents Examined by Evan G Clinton
  • Patent number: 10998208
    Abstract: Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head coupleable to a vacuum source and positioned to releasably attach to the semiconductor die at a pick station. The system still further includes a cooling member coupleable to a cold fluid source and configured to direct a cold fluid supplied by the cold fluid source toward the support substrate at the pick station. The cold fluid cools a die attach region of the substrate where the semiconductor die is attached to the substrate to facilitate removal of the semiconductor die.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy E. Minnich, Benjamin L. McClain, Travis M. Jensen
  • Patent number: 10983181
    Abstract: A magnetic sensor whose output characteristic is less sensitive to the environmental temperature is provided. Magnetic sensor 1 has free layer 24 whose magnetization direction changes in response to an external magnetic field, pinned layer 22 whose magnetization direction is fixed with respect to the external magnetic field, spacer layer 23 that is located between pinned layer 22 and free layer 24 and that exhibits a magnetoresistance effect, and at least one magnet film 25 that is disposed on a lateral side of free layer 24 and that applies a bias magnetic field to free layer 24. A relationship of 0.7 ?TC_HM/TC_FL?1.05 is satisfied, where TC_HM is Curie temperature of the magnet film, and TC_FL is Curie temperature of the free layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: April 20, 2021
    Assignee: TDK Corporation
    Inventors: Kenichi Takano, Yuta Saito, Hiraku Hirabayashi
  • Patent number: 10978580
    Abstract: A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 13, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Kohei Shinsho
  • Patent number: 10978359
    Abstract: Provided is an SiC substrate evaluation that includes irradiating a first surface of an SiC substrate which is cut out from an SiC ingot with excitation light before an epitaxial film is laminated on the first surface to perform photoluminescence measurement.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 13, 2021
    Assignee: SHOWA DENKO K.K.
    Inventor: Shunsuke Noguchi
  • Patent number: 10964554
    Abstract: The present disclosure relates to a packaging process to enhance performance of a wafer-level package. The disclosed package includes multiple mold compounds, a multilayer redistribution structure, and a thinned die with a device layer and die bumps underneath the device layer. The multilayer redistribution structure includes package contacts at a bottom of the multilayer redistribution structure and redistribution interconnects connecting the die bumps to the package contacts. A first mold compound resides around the thinned die to encapsulate sidewalls of the thinned die, and extends beyond a top surface of the thinned die to define an opening over the thinned die. A second mold compound resides between the multilayer redistribution structure and the first mold compound to encapsulate a bottom surface of the device layer and each die bump. A third mold compound fills the opening and is in contact with the top surface of the thinned die.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 30, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Jonathan Hale Hammond, Julio C. Costa
  • Patent number: 10954122
    Abstract: A method for bonding at least three substrates to form a substrate stack, wherein the substrate stack has at least one lowermost substrate a middle substrate, and an upper substrate. The method includes the following steps: aligning the middle substrate to the lowermost substrate and bonding the middle substrate to the lowermost substrate, then aligning the upper substrate and bonding the upper substrate to the middle substrate, wherein the upper substrate is aligned to the lowermost substrate.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: March 23, 2021
    Assignee: EV Group E. Thallner GmbH
    Inventors: Thomas Wagenleitner, Thomas Glinsner, Harald Zaglmayr
  • Patent number: 10950518
    Abstract: The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 16, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Jonathan Hale Hammond, Julio C. Costa, Jon Chadwick
  • Patent number: 10950475
    Abstract: Methods and apparatus for processing a substrate are provided. The apparatus, for example, can include a process chamber comprising a chamber body defining a processing volume and having a view port coupled to the chamber body; a substrate support disposed within the processing volume and having a support surface to support a substrate; and an infrared temperature sensor (IRTS) disposed outside the chamber body adjacent the view port to measure a temperature of the substrate when being processed in the processing volume, the IRTS movable relative to the view port for scanning the substrate through the view port.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Vinodh Ramachandran, Ananthkrishna Jupudi, Cheng-Hsiung Tsai, Yueh Sheng Ow, Preetham P. Rao, Ribhu Gautam, Prashant Agarwal
  • Patent number: 10950543
    Abstract: The semiconductor device includes a first semiconductor substrate, a first wiring layer, a second wiring layer, a second semiconductor substrate, a first conductive portion, and a second conductive portion. The first wiring layer includes a first electrode pad and a first inductor electrically connected with each other. The second wiring layer includes a second inductor and a second electrode pad electrically connected with each other. The first conductive portion is formed in the second semiconductor substrate, the second wiring layer, and the first wiring layer so as to reach the first electrode pad from the back surface of the second semiconductor substrate. The second conductive portion is formed in the second semiconductor substrate and the second wiring layer so as to reach the second electrode pad from the back surface of the second semiconductor substrate. The first inductor and the second inductor are disposed so as to face each other.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: March 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba
  • Patent number: 10950435
    Abstract: A SiC substrate (1) has an off angle ?°. A SiC epitaxial layer (2) having a film thickness of Tm ?m is provided on the SiC substrate (1). Triangular defects (3) are formed on a surface of the SiC epitaxial layer (2). A density of triangular defects (3) having a length of Tm/Tan ?×0.9 or more in a substrate off direction is denoted by A. A density of triangular (3) defects having a length smaller than Tm/Tan ?×0.9 in the substrate off direction is denoted by B. B/A?0.5 is satisfied.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Yasuhiro Kimura, Yoichiro Mitani
  • Patent number: 10949638
    Abstract: The invention relates to a manufacturing process of a pixel array of a thermal pattern sensor comprising the steps of: providing a substrate; depositing a first layer of electrically conductive material, including depositing electrically conductive tracks, depositing of connector pins and depositing a ground strip; depositing of second layer of pyroelectric material covering the tracks and leaving at least part of the connector pins free; depositing of third layer of electrically conductive material; depositing of fourth layer of dielectric material in contact with the third layer; depositing of a fifth layer including electrically conductive heating tracks; depositing of a sixth protective layer, wherein the step of depositing the second and/or third and/or fourth and/or sixth layer is carried out by slot-die coating.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 16, 2021
    Assignees: IDEMIA IDENTITY & SECURITY FRANCE, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Francois Mainguet, Joel-Yann Fourre, Christophe Serbutoviez, Mohammed Benwadih
  • Patent number: 10943898
    Abstract: A method for fabricating a semiconductor device includes, for a substrate having a first region protected by a cap layer, forming a first device on a second region of the substrate. The substrate includes an insulator layer disposed between a first semiconductor layer and a second semiconductor layer each including a first semiconductor material. The method further includes forming a second device on the first region, including forming one or more transistors each having a channel formed from a second semiconductor material different from the first semiconductor material.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Zhang, Ko-Tao Lee, Todd E. Takken, Paul W. Coteus, Andrew Ferencz
  • Patent number: 10943782
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate, forming a hole penetrating the mold structure, forming on the substrate a second semiconductor layer filling the hole, and irradiating a laser onto the second semiconductor layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-jung Kim, Kiseok Lee, Keunnam Kim, Yoosang Hwang
  • Patent number: 10937651
    Abstract: A laser annealing method includes: step A of providing a substrate having an amorphous semiconductor film formed on a surface thereof; and step B of selectively irradiating a portion of the amorphous semiconductor film with laser light. The step B includes a step of simultaneously forming, in the portion, two molten regions that have elongate shapes congruent to each other and are arranged in line symmetry with each other.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 2, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Masakazu Tanaka, Shinji Koiwa, Kouichi Karatani, Akihiro Shinozuka, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10937658
    Abstract: An LED wafer is formed from a sapphire substrate having a front side. A plurality of crossing division lines are formed on the front side of the sapphire substrate to thereby define a plurality of separate regions where a plurality of LEDs are respectively formed. An LED wafer processing method includes preparing a V-blade having an annular cutting edge whose outer circumferential portion has a V-shaped cross section, rotatably mounting the V-blade in a cutting unit, holding the LED wafer on a holding table with the back side of the LED wafer exposed upward, and then relatively moving the cutting unit and the holding table to form a chamfered portion on the back side of the LED wafer along an area corresponding to each division line formed on the front side of the LED wafer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 2, 2021
    Assignee: DISCO CORPORATION
    Inventor: Makiko Ohmae
  • Patent number: 10923556
    Abstract: A display device includes a substrate which includes a display area and a non-display area, a pixel unit which is provided in the display area and includes a plurality of pixel columns, and data lines which are respectively connected to the pixel columns and apply data signals to the pixel columns. The non-display area includes a fanout area, a bent area, and a pad area which are sequentially arranged. The respective data lines are disposed on different layers in the fanout area and the pad area. A resulting display device can reduce resistance deviation between data signals in a first data line and a second data line, thereby reducing vertical line defects.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: February 16, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joong Soo Moon, Sun Ja Kwon, Min Woo Byun, Seung Yeon Cho
  • Patent number: 10916563
    Abstract: A semiconductor device includes a substrate having a cell region and an extension region, channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, gate electrode layers surrounding the channel structures and stacked to be spaced apart from each other in the first direction and to extend in a second direction substantially perpendicular to the first direction, and word line cuts cutting the gate electrode layers in the first direction and continuously extending in the second direction. At least one of the word line cuts is an extension word line cut with an extension portion having an area that is different from those of the remaining word line cuts located at the same level as the at least one word line cut in a predetermined region extending in the second direction.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Woo Kim, Joon Young Kwon, Jung Hwan Lee, Jung Tae Sung, Ji Min Shin
  • Patent number: 10906274
    Abstract: The present disclosure relates to a laminate substrate with sintered components. The disclosed laminate substrate includes a substrate body having an opening through the substrate body, a first foil layer, a sintered base component, and a sintered contact film. The first foil layer is formed underneath the substrate body, such that a first portion of the first foil layer fully covers the bottom of the opening. The sintered base component is formed within the opening and over the first portion of the first foil layer. Herein, the sintered base component has a dielectric constant between 10 and 500, or has a relative permeability greater than 5. The sintered contact film is formed over the sintered base component. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on the bottom, and by the sintered contact film on the top.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 2, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Tarak A. Railkar, Deepukumar M. Nair, Jeffrey Dekosky
  • Patent number: 10910218
    Abstract: A SiC substrate (1) has an off angle ?°. A SiC epitaxial layer (2) having a film thickness of Tm ?m is provided on the SiC substrate (1). Triangular defects (3) are formed on a surface of the SiC epitaxial layer (2). A density of triangular defects (3) having a length of Tm/Tan ?×0.9 or more in a substrate off direction is denoted by A. A density of triangular (3) defects having a length smaller than Tm/Tan ?×0.9 in the substrate off direction is denoted by B. B/A?0.5 is satisfied.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: February 2, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Yasuhiro Kimura, Yoichiro Mitani
  • Patent number: 10903121
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Karthik Balakrishnan, James S. Papanu