Patents Examined by Evan G Clinton
  • Patent number: 11276588
    Abstract: A method of processing a wafer includes a protective member affixing step of affixing a protective member whose area covers a face side or a reverse side of the wafer to the wafer, and after the protective member affixing step has been carried out, a ring-shaped stiffener removing step of removing a ring-shaped stiffener from the wafer. The ring-shaped stiffener removing step includes a ring-shaped stiffener separating step of dividing the wafer along an outer circumference of a device region to separate the device region and the ring-shaped stiffener from each other, and after the ring-shaped stiffener separating step has been carried out, a removing step of processing the ring-shaped stiffener with a grindstone to remove the ring-shaped stiffener from the wafer while a processing fluid is being supplied to the wafer.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: March 15, 2022
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 11251071
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Patent number: 11251142
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 11251093
    Abstract: An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: February 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Younsung Choi, Steven Lee Prins
  • Patent number: 11245050
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: February 8, 2022
    Assignee: Soitec
    Inventor: David Sotta
  • Patent number: 11217546
    Abstract: A method includes attaching a voltage regulator to a first redistribution structure of a first package. A second redistribution structure is formed over the voltage regulator, the voltage regulator being embedded in the second redistribution structure. The first substrate is attached to the second redistribution structure to form a second package including the first package. A first voltage may be provided to the second redistribution structure and through the second redistribution structure to the voltage regulator. The voltage regulator regulates the first voltage into a second voltage and provides the second voltage through the first redistribution structure to a first device die, where an output of the voltage regulator is attached directly to the first redistribution structure.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chien-Hsun Chen
  • Patent number: 11217479
    Abstract: A multiple metallization scheme in conductive features of a device uses ion implantation in a first metal layer to make a portion of the first metal layer soluble to a wet cleaning agent. The soluble portion may then be removed by a wet cleaning process and a subsequent second metal layer deposited over the first metal layer. An additional layer may be formed by a second ion implantation in the second metal layer may be used to make a controllable portion of the second metal layer soluble to a wet cleaning agent. The soluble portion of the second metal layer may be removed by a wet cleaning process. The process of depositing metal layers, implanting ions, and removing soluble portions, may be repeated until a desired number of metal layers are provided.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Ying Ho, Fang-I Chih, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11195875
    Abstract: An X-ray detecting panel and a method of operating the same, and an x-ray detecting device are provided. The X-ray detecting panel includes an array substrate which includes a plurality of gate lines and a plurality of signal lines intersecting with each other to divide the array substrate into a plurality of photosensitive cells, each of which comprises a thin film transistor, and the plurality of photosensitive cells comprises one or more first photosensitive cells and one or more second photosensitive cells, the thin film transistor of the first photosensitive cell is disposed at a first side of the first photosensitive cell, the thin film transistor of the second photosensitive cell is disposed at a second side of the second photosensitive cell, and the first side is opposite to the second side.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 7, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jian Lin, Yong Zhang, Gang Hua, Haobo Fang, Limin Zhang, Lu Bai, Lei Mi, Zhiying Bao, Yanna Xue
  • Patent number: 11164799
    Abstract: A method for forming a semiconductor structure is provided. The method including epitaxially growing a first source drain on the semiconductor structure between a first lower fin in a first region of the semiconductor structure and a second lower fin in a second region of the semiconductor structure, forming a first spacer layer on the first source drain, where a lower horizontal surface of the first spacer layer is coplanar with an upper horizontal surface of the first source drain, forming a lower gate stack surrounding the first lower fin and surrounding the second lower fin on exposed surfaces of the semiconductor structure, where a lower horizontal surface of the gate stack is coplanar with an upper horizontal surface of the first spacer layer, forming an interlayer dielectric on exposed surfaces of the first spacer layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Chen Zhang, Kangguo Cheng, Tenko Yamashita
  • Patent number: 11158676
    Abstract: A sensor includes an anode and a cathode, and a near-infrared photoelectric conversion layer between the anode and the cathode. The near-infrared photoelectric conversion layer is configured to absorb light of at least a portion of a near-infrared wavelength spectrum and convert the absorbed light into an electrical signal. The near-infrared photoelectric conversion layer includes a first material having a maximum absorption wavelength in the near-infrared wavelength spectrum and a second material forming a pn junction with the first material and having a wider energy bandgap than an energy bandgap of the first material. The first material is included in the near-infrared photoelectric conversion layer in a smaller amount than the second material.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Seok Leem, Rae Sung Kim, Hyesung Choi, Ohkyu Kwon, Changki Kim, Hwang Suk Kim, Bum Woo Park, Jae Jun Lee
  • Patent number: 11155913
    Abstract: An evaporation mask plate, a manufacturing method thereof and an evaporation method are provided. The evaporation mask plate includes a body, a plurality of evaporation cutout regions formed in the body, and a plurality of shielding members arranged on the body. Each shielding member is arranged between two adjacent evaporation cutout regions.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: October 26, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hongguang Yuan, Pilgeun Chun, Yan Hu
  • Patent number: 11148938
    Abstract: According to one embodiment, a controller is configured to calculate a matching rate of grid shapes between each semiconductor wafer of a first semiconductor wafer group and each semiconductor wafer of a second semiconductor wafer group, and generate pairing information, into which combinations of semiconductor wafers used in calculation of matching rates are registered when the matching rates fall within a predetermined range. Further, the controller is configured to select a first semiconductor wafer to be held by a first semiconductor wafer holder from the first semiconductor wafer group, and select a second semiconductor wafer from semiconductor wafers of the second semiconductor wafer group, which are paired with the first semiconductor wafer, with reference to the pairing information.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Sho Kawadahara
  • Patent number: 11152390
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Patent number: 11145530
    Abstract: The integrated circuit assembly can include: a semiconductor and a substrate (e.g., PCB). The integrated circuit assembly can optionally include: a compliant connector, a thermal management, and a securing element. The semiconductor 210 can include a first alignment feature. (e.g., orifice). The substrate can include a second alignment feature (e.g., alignment target) and conductive pads. The substrate can optionally include a cavity.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: October 12, 2021
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Tim Botsford, Philip Ferolito, Paul Kennedy
  • Patent number: 11137685
    Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11114599
    Abstract: Electronic devices including a layer of polymeric material and solid semiconductor dies partially embedded in the layer are provided. The dies have first ends projecting away from the first major surface of the layer. The electronic devices can be formed by sinking the first ends of the dies into a major surface of a liner. A flowable polymeric material is filled into the space between the dies and solidified to form the layer of polymeric material. The first ends of the dies are exposed by delaminating the liner from the first ends of the dies. Electrical conductors are provided on the layer to connect the first ends of the dies.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: September 7, 2021
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ankit Mahajan, Mikhail L. Pekurovsky, Matthew S. Stay, Shawn C. Dodds, Thomas J. Metzler, Matthew R. D. Smith, Saagar A. Shah, Jae Yong Lee, James F. Poch, Roger W. Barton
  • Patent number: 11069590
    Abstract: The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Jonathan Hale Hammond, Julio C. Costa, Jon Chadwick
  • Patent number: 11056465
    Abstract: Semiconductor packages including active die stacks, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes an active die having a top surface covered by a molding compound, and a bonding pad attached to only one interconnect wire. A method of fabricating the semiconductor package includes bridging a pair of dies stacks by the interconnect wire, and dividing the interconnect wire to form separate wire segments attached to respective die stacks.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventor: Yi Xu
  • Patent number: 11056497
    Abstract: A method used in forming a memory array comprises forming a conductive tier atop a substrate, with the conductive tier comprising openings therein. An insulator tier is formed atop the conductive tier and the insulator tier comprises insulator material that extends downwardly into the openings in the conductive tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the insulator tier. Strings comprising channel material that extend through the insulative tiers and the wordline tiers are formed. The channel material of the strings is directly electrically coupled to conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Damir Fazil, Nancy M. Lomeli
  • Patent number: 11056547
    Abstract: An organic light-emitting display device includes: a substrate; a pixel electrode on the substrate; a pixel defining layer having a first opening exposing a center portion of the pixel electrode; a barrier layer on the pixel defining layer; an intermediate layer including a first common layer, a first emissive layer, and a second common layer sequentially arranged on the pixel electrode, the pixel defining layer, and the barrier layer; and a first opposite electrode covering the intermediate layer. The barrier layer has a second opening that is larger than the first opening and has an undercut structure.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 6, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Duckjung Lee