Abstract: An organic light emitting diode display device includes a substrate including a display region, wherein a plurality of pixel regions are defined in the display region; a first electrode over the substrate and in each of the plurality of pixel regions; a bank including a lower layer and an upper layer on the first electrode, the lower layer disposed on edges of the first electrode and having a first width and a first thickness, the upper layer disposed on the lower layer and having a second width smaller than the first width; an organic emitting layer on the first electrode and a portion of the lower layer; and a second electrode on the organic emitting layer and covering an entire surface of the display region.

Abstract: In some embodiments, a metal oxide second electrode material is formed as part of a MIM DRAM capacitor stack. The second electrode material is doped with one or more dopants. The dopants may influence the crystallinity, resistivity, and/or work function of the second electrode material. The dopants may be uniformly distributed throughout the second electrode material or may be distributed with a gradient in their concentration profile.

Abstract: Disclosed are a light emitting diode array on a wafer level and a method of forming the same. The light emitting diode array includes a growth substrate; a plurality of light emitting diodes arranged on the substrate, wherein each of the plurality of light emitting diodes has a first semiconductor layer, an active layer and a second semiconductor layer; and a plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of an identical material, wherein each of the plurality of upper electrodes is electrically connected to the first semiconductor layer of a respective one of the light emitting diodes. At least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes, and another of the upper electrodes is insulated from the second semiconductor layer of an adjacent one of the light emitting diodes.

Abstract: A LED pixel unit circuit and a display panel. The circuit comprises a driving module (31) which is provided with a driving control unit (311). The driving control unit (311) comprises a matching TFT (T4) whose threshold voltage is matched with the threshold voltage of the driving TFT (DTFT), is located between the first switching element (T1) and the first capacitor (C1), and is configured to control charging and discharging of the first capacitor (C1) so as to write the threshold voltage of the matching TFT (T4) and a new data voltage into the first capacitor (C1) while eliminating the original data voltage in the first capacitor (C1) and thereby compensate for the threshold voltage of the driving TFT (DTFT). The circuit can solve the problem of brightness non-uniformity of the display panel due to different threshold voltages of the TFTs, and also integrate a touch screen circuit into the pixel unit circuit to realize a touch function of the LED display panel.

Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.

Abstract: A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.

Abstract: This invention discloses methods and apparatus to form organic semiconductor transistors upon three-dimensionally formed insert devices. In some embodiments, the present invention includes incorporating the three-dimensional surfaces with organic semiconductor-based thin film transistors, electrical interconnects, and energization elements into an insert for incorporation into ophthalmic lenses. In some embodiments, the formed insert may be directly used as an ophthalmic device or incorporated into an ophthalmic device.

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Abstract: An organic light emitting diode (OLED) display includes: a first substrate including a display area and a non-display area; a driving element on the display area of the first substrate, and including a driving thin film transistor, a switching thin film transistor, and a capacitor; a circuit unit on the non-display area of the first substrate; an organic light emitting element on the driving element, and including a pixel electrode, an organic emission layer, and a common electrode; an inorganic protective layer covering the circuit unit and the common electrode of the organic light emitting diode; a sealing member on the inorganic protective layer in the non-display area of the first substrate; and a second substrate on the sealing member.

Abstract: A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract: A manufacturing method of a BSI image sensor includes providing a substrate having a plurality of photo-sensing elements and a plurality of multilevel interconnects formed on a first side of the substrate; forming a redistribution layer (RDL) and a first insulating layer covering the RDL on the front side of the substrate; providing a carrier wafer formed on the front side of the substrate; forming a color filter array (CFA) on a second side of the substrate, the second side being opposite to the first side; removing the carrier wafer; and forming a first opening in the first insulating layer for exposing the RDL.

Abstract: In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump.

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.

Abstract: An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode.

Abstract: According to embodiments of the invention, a TFT array substrate, a manufacturing method of the TFT array substrate and a display device are provided. The method comprises: depositing a metal film on a substrate, and forming a gate electrode and a gate line; forming a gate insulating layer and a passivation layer on the substrate; depositing a transparent conductive layer, a first source/drain metal layer and a first ohmic contact layer, and forming a drain electrode, a pixel electrode, a data line, and a first ohmic contact layer pattern provided on the drain electrode; and depositing a semiconductor layer, a second ohmic contact layer and a second source/drain metal layer, and forming a source electrode, a second ohmic contact layer pattern provided below the source electrode, and a semiconductor channel between the source electrode and the drain electrode.

Abstract: The present disclosure relates to a touch panel, and more particularly, to a kind of touch panel which actualizes various touch response functions on a same surface and a fabrication method thereof. The touch panel includes an upper cover substrate, a first electrode array, a patterned mask layer, and at least a second electrode array. The upper cover substrate includes a display area and a peripheral area surrounding the display area. The first electrode array is disposed corresponding to the display area. The patterned mask layer is disposed corresponding to the peripheral area. At least a second electrode array is disposed corresponding to a first patterned area of the patterned mask layer. A fabricating method for the touch panel is also provided.

Abstract: In one embodiment, a method of forming a MEMS device includes providing a silicon wafer with a base layer and an intermediate layer above an upper surface of the base layer. A first electrode is defined in the intermediate layer and an oxide portion is provided above an upper surface of the intermediate layer. A cap layer is provided on an upper surface of the oxide portion and a second electrode is defined in the cap layer. The method further includes etching the oxide portion to form a cavity such that when the second electrode and the cavity are projected onto the intermediate layer, the projected second electrode encompasses the projected cavity.

Abstract: A semiconductor device has: a first transparent electrode, a drain electrode, and a source electrode formed on a substrate; an oxide layer joined electrically to the source electrode and the drain electrode and containing a semiconductor region; an insulating layer formed on the oxide layer and the first transparent electrode; a gate electrode formed on the insulating layer; and a second transparent electrode formed so as to overlap at least a part of the first transparent electrode with the insulating layer interposed therebetween. The oxide layer and the first transparent electrode are formed of the same oxide film.