Abstract: Fabrication methods for a device structure and device structures. A trench isolation region is formed that bounds an active device region of a semiconductor substrate. A first semiconductor layer is formed on the active device region and on the trench isolation region. A first airgap is formed between the first semiconductor layer and the active device region. A second airgap is formed between the first semiconductor layer and the trench isolation region. The first airgap extends into the active device region such that the height of the first airgap is greater than the height of the second airgap.

Abstract: A power semiconductor module includes a power electronics substrate having a first surface, a second surface opposite the first surface, a first longitudinal side, a second longitudinal side opposite the first longitudinal side, a module frame, which is arranged to enclose the power electronics substrate, at least one power terminal which is arranged at the first longitudinal side and extends through the module frame, a further terminal, which is arranged at the second longitudinal side and extends through the module frame, at least one power semiconductor component which is arranged on the first surface of the power electronics substrate and is electrically connected to at least one power terminal, and at least one current sensor which is designed to measure a current in a power terminal. The at least one current sensor is arranged on the power terminal and has a signal output connected to the further terminal.

Abstract: A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a dielectric material layer, a second conductive wiring layer, a second conductive pillar layer, and a first molding compound layer. The first conductive wiring layer has a first surface and a second surface opposite to the first surface. The first conductive pillar layer is disposed on the first surface of the first conductive wiring layer, wherein the first conductive wiring layer and the first conductive pillar layer are disposed inside the dielectric material layer. The second conductive wiring layer is disposed on the first conductive pillar layer and the dielectric material layer. The second conductive pillar layer is disposed on the second conductive wiring layer, wherein the second conductive wiring layer and the second conductive pillar layer are disposed inside the first molding compound layer.

Abstract: Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect to a waveguide core to reduce effects of dark current on a detected optical signal.

Abstract: A method comprises growing a channel layer comprising a first channel region and a second channel region, depositing a first hard mask layer over the channel layer, patterning the first hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, depositing a first cap layer over the first delta doping layer, depositing a second hard mask layer over the channel layer, wherein the first cap layer is embedded in the second hard mask layer, patterning the second hard mask layer and the first hard mask layer to expose the second channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region and applying a first diffusion process to the first delta doping layer and the second delta doping layer.

Abstract: A schottky barrier diode includes an n? type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n? type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n? type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n? type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n? type epitaxial layer.

Abstract: The present invention provides a thin film transistor (TFT) array substrate and a method for manufacturing the same. A transparent and electrically conductive layer and a first metal layer are deposited on a substrate, and a first multi tone mask is utilized to form gate electrodes and common electrodes. A gate insulating layer, a semiconductor layer and a second metal layer are deposited on the substrate, and a second multi tone mask is utilized to form source electrodes, drain electrodes and pixel electrodes. The present invention can simplify the manufacturing process thereof.

Abstract: A resistive memory cell, e.g., CBRAM or ReRAM cell, may include a top electrode an a trench-shaped bottom electrode structure defining a bottom electrode connection and a sidewall extending from a first sidewall region adjacent the bottom electrode connection to a tip region defining a tip surface facing generally away from the bottom electrode connection, and wherein the tip surface facing away from the bottom electrode connection has a tip thickness that is less than a thickness of the first sidewall region adjacent the bottom electrode connection. An electrolyte switching region is arranged between the top electrode and the bottom electrode sidewall tip region to provide a path for the formation of a conductive filament or vacancy chain from the bottom electrode sidewall tip surface of the top electrode, via the electrolyte switching region, when a voltage bias is applied to the resistive memory cell.

Abstract: A light-emitting device includes: a substrate including an upper surface, wherein the upper surface includes an ion implantation region; a semiconductor layer formed on the upper surface; a light-emitting stack formed on the semiconductor layer; and a plurality of scattering cavities formed between the semiconductor layer and the upper surface in accordance with the ion implantation region.

Abstract: A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap; forming a dielectric layer over the silicon fin and the gate; removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin; recessing the silicon fin; and removing the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin.

Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.

Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode having an upper surface coplanar with a top surface of the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the source/drain region.

Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.

Abstract: A light emitting device including a support substrate, an adhesive layer on the support substrate, a conductive layer on the adhesive layer, a light emitting structure on the conductive layer, the light emitting structure including a first semiconductor layer containing AlGaN, an active layer, and a second semiconductor layer containing AlGaN, a first electrode on the light emitting structure, a metal layer disposed under the conductive layer and at an adjacent region of the conductive layer, and a passivation layer disposed on a side surface of the light emitting structure, wherein the first electrode is vertically non-overlapped with the conductive layer, wherein the conductive layer includes a first layer and a second layer on the first layer, wherein the second layer directly contacts with the light emitting structure, wherein the metal layer directly contacts with the light emitting structure, wherein the metal layer is expanded to an outer area of the light emitting structure, and wherein the passivatio

Abstract: The disclosure relates to method and apparatus for micro-contact printing of micro-electromechanical systems (“MEMS”) in a solvent-free environment. The disclosed embodiments enable forming a composite membrane over a parylene layer and transferring the composite structure to a receiving structure to form one or more microcavities covered by the composite membrane. The parylene film may have a thickness in the range of about 100 nm-2 microns; 100 nm-1 micron, 200-300 nm, 300-500 nm, 500 nm to 1 micron and 1-30 microns. Next, one or more secondary layers are formed over the parylene to create a composite membrane. The composite membrane may have a thickness of about 100 nm to 700 nm to several microns. The composite membrane's deflection in response to external forces can be measured to provide a contact-less detector. Conversely, the composite membrane may be actuated using an external bias to cause deflection commensurate with the applied bias.

Abstract: In some embodiments, the present disclosure pertains to methods of preparing graphene nanoribbons from a graphene film associated with a meniscus, where the method comprises patterning the graphene film while the meniscus acts as a mask above a region of the graphene film, and where the patterning results in formation of graphene nanoribbons from the meniscus-masked region of the graphene film. Additional embodiments of the present disclosure pertain to methods of preparing wires from a film associated with a meniscus, where the method comprises patterning the film while the meniscus acts as a mask above a region of the film, and where the patterning results in formation of a wire from the meniscus-masked region of the film. Additional embodiments of the present disclosure pertain to chemical methods of preparing wires from water-reactive materials.

Abstract: The present invention features methods for forming a field effect transistor on a semiconductor substrate having gate, source and drain regions, with the gate region having a lateral gate channel. A plurality of spaced-apart trenches or through semiconductor vias (TSV) each having an electrically conductive plug formed therein in electrical communication with the gate, source and drain regions are configured to lower the resistance of the bottom source. A contact trench is formed adjacent to the source region and shorts the source region and a body region. A source contact is in electrical communication with the source region; and a drain contact in electrical communication with the drain region, with the source and drain contacts being disposed on opposite sides of the lateral gate channel.

Abstract: A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging.

Abstract: A thermally tempered glass substrate for transient electronic systems (i.e., including electronic devices that visually disappear when triggered to do so) including two or more fused-together glass structures having different coefficient of thermal expansion (CTE) values disposed in an intermixed arrangement manner that generates and stores potential energy in the form of residual, self-equilibrating internal stresses. In alternative embodiments the substrate includes laminated glass sheets, or glass elements (e.g., beads or cylinders) disposed in a glass layer. A trigger device causes an initial fracture in the thermally tempered glass substrate, whereby the fracture energy nearly instantaneously travels throughout the thermally tempered glass substrate, causing the thermally tempered glass substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. Patterned fracture features are optionally provided to control the final fractured particle size.

Abstract: An optoelectronic component including a housing having at least one first cutout and at least one first semiconductor chip arranged in the first cutout, wherein the first cutout is a first reflector that reflects radiation generated during operation of the first semiconductor chip, the first reflector has a surface, and the surface has a targeted setting of an emission characteristic of the radiation emitted by the first semiconductor chip during operation.