Abstract: A semiconductor device includes a semiconductor body having first and second opposite surfaces along a vertical direction, and an active diode area. The active diode area includes: a p-doped anode region adjoining the first surface; an n-doped drift region between the anode region and the second surface; an n-doped cathode contact region adjoining the second surface; a p-doped injection region adjoining the second surface and the cathode contact region; and a p-doped auxiliary region between the drift region and the cathode contact region. The auxiliary region includes first and second sub-regions. In a top view, the first sub-region covers at least part of the injection region and the second sub-region covers at least part of the cathode contact region. In the top view, the auxiliary region includes a plurality of openings covering from 0.1% to an 20% of a surface area of the active diode area at the second surface.

Abstract: A semiconductor device that can be subjected to multipoint measurement is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a first multiplexer, a second multiplexer, m (m is an integer of 1 or more) analog switches electrically connected to the first multiplexer, and n (n is an integer of 1 or more) analog switches electrically connected to the second multiplexer. The second layer includes m×n transistors. Each of the m analog switches is electrically connected to n transistors, and each of the n analog switches is electrically connected to m transistors.

Abstract: An input feedthrough (8) and an output feedthrough (9) provided on the substrate (3) are wire-connected to an input pad (5) and an output pad (6) of the semiconductor chip (4) respectively. A metal seal ring (12) is provided on the substrate (3) is electrically connected to the metal plate (1) by a through-hole (15). A conductive cap (14) is bonded to the metal seal ring (12) and covers a place above the semiconductor chip (4). Both ends of an isolation metal wire (13) are electrically connected to the metal plate (1) and a loop comes into contact with a lower surface of the conductive cap (14). The isolation metal wire (13) constitutes an isolation wall partitioning an inner space into a region including the input feedthrough (8) and a region including the output feedthrough (9).

Abstract: A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.

Abstract: A display device includes a trench, which includes: first and second trench lines respectively located between neighboring column lines and between neighboring row lines, wherein the first trench line includes a first side groove in a column direction, and first and second corner grooves connected between adjacent first side grooves, forming an isosceles portion protruding to one side in a row direction, having second and first diagonal directions, respectively, and connected to each other at a first contact point, wherein the second trench line includes a second side groove in the row direction, and the first and second corner grooves connected between adjacent second side grooves, forming an isosceles portion protruding to one side in the column direction, and connected to each other at a second contact point, wherein the protruding isosceles portions of the first and second trench lines share the first corner groove.

Abstract: [Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin. [Solution] A semiconductor module 1 includes semiconductor chips 14a to 14d, sealing resin 18 configured to seal the semiconductor chips 14a to 14d, a case 11 including a casting area 117u, first portions 111 and 112, and second portions 113 and 114, wire wirings 101a to 101j and 102a to 102i sealed in the sealing resin 18 while being located closer to the first portion 111 and connected to the semiconductor chips 14a to 14d, and recessed portions 131a, 131b, 132a, and 132b formed on the second portions 113 and 114 between a virtual surface VSu and the first portion 112.

Abstract: A semiconductor device includes a bit line extending in a first direction on a substrate. A first insulating pattern is disposed on the bit line. A channel pattern is disposed on an upper side of the bit line and a lateral side of the first insulating pattern. The channel pattern includes an oxide semiconductor material. A gate insulating pattern is disposed on the channel pattern. Word lines are disposed on the gate insulating pattern. A second insulating pattern is disposed on the word lines. A landing pad is disposed on the channel pattern. An interlayer insulating layer disposed between the bit line and the channel pattern.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures. The integrated circuit structure also includes a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures. The second pitch is greater than the first pitch.

Abstract: A display device comprises a substrate, a sub-pixel disposed on the substrate and that includes a pixel electrode, a light emitting layer, and a common electrode, a pixel defining layer that defines the sub-pixel, a capping layer disposed on the pixel defining layer, a micro lens disposed on the capping layer and that overlaps the sub-pixel; and a total reflection pattern disposed on the capping layer and that overlaps the pixel defining layer and surrounds the micro lens. The micro lens has a refractive index greater than a refractive index of the total reflection pattern and less than or equal to a refractive index of the capping layer.

Abstract: A method for manufacturing a semiconductor element includes preparing a semiconductor wafer that includes a substrate including a Ga2O3-based semiconductor and an epitaxial layer including a Ga2O3-based semiconductor and located on the substrate, fixing the epitaxial layer side of the semiconductor wafer to a support substrate, thinning the substrate of the semiconductor wafer fixed to the support substrate, after the thinning of the substrate, forming an electrode on a lower surface of the substrate, bonding or forming a support metal layer on a lower surface of the electrode of the semiconductor wafer, and dicing the semiconductor wafer into individual pieces, thereby obtaining plural semiconductor elements each including the support metal layer. Thermal conductivity of the support metal layer is higher than thermal conductivity of the substrate.

Abstract: A diamond-based particle detector includes a diamond substrate that includes a first side and a second side; a first side first doped layer contacting the first side of the diamond substrate; a first metal contact contacting the first side first doped layer, a first side intrinsic diamond layer contacting the first side first doped layer, (i) a second side first doped layer or (ii) a second side intrinsic diamond layer contacting the second side of the diamond substrate; and a second metal contact contacting (i) the second side first doped layer or (ii) the second side intrinsic diamond layer.

Abstract: Disclosed is a semiconductor structure. The semiconductor structure includes a support structure, and a first dielectric layer and a growth substrate sequentially formed on the support structure, where a gravity center of the support structure and a gravity center of the growth substrate are disposed in a staggered manner, so that the direct contact between the growth substrate and the graphite disk can be avoided, a centrifugal force on the growth substrate exerted by the graphite disk to the support structure can be transferred, thereby further ensuring a quality of the growth substrate, and significantly reducing a probability of cracking to ensure a crystal quality of a subsequent epitaxial layer. The support structure is formed at the bottom of the growth substrate, so that a mechanical strength of the semiconductor structure can be effectively improved, a stability can be enhanced, and a deformation of the semiconductor structure can be suppressed.

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

Abstract: A display device includes a first conductive layer; a first insulating layer on the first conductive layer; a semiconductor layer disposed on the first insulating layer and electrically connected to the first conductive layer; a second conductive layer disposed on the semiconductor layer and electrically connected to the first conductive layer; and light emitting elements on the second conductive layer. A thickness of a part of the first insulating layer in a first area, which overlaps the semiconductor layer in a plan view, is different from a thickness of another part of the first insulating layer in a second area, which is exposed by the semiconductor layer.

Abstract: A thermal management system includes a baseplate assembly and a flow system. The baseplate assembly includes a baseplate and a semiconductor die. The flow system includes a submerged jet impingement assembly for direct semiconductor die cooling, a first flow path extending over the semiconductor die via the submerged jet impingement assembly, and a second flow path in thermal contact with the baseplate, the flow system including a fluid flowing through the first flow path and the second flow path. The flow system is configured to direct the fluid to the upper semiconductor surface of the semiconductor die via the first flow path and to the baseplate via the second flow path so as to transfer heat away from the semiconductor die and from the baseplate so as to cool the baseplate assembly.

Abstract: An infrared light emitter includes a substrate, a first light-emitting layer, a blocking layer, and a second light-emitting layer. The second light-emitting layer is disposed on the substrate, the blocking layer is disposed on the second light-emitting layer, and the first light-emitting layer is disposed on the blocking layer. The first light-emitting layer, the blocking, and the second light-emitting layer form a P-N-P junction or an N-P-N junction. The first light-emitting layer and the blocking layer form a first electroluminescent unit, and the blocking layer and the second light-emitting layer form a second electroluminescent unit. The first electroluminescent unit and the second electroluminescent unit build two back-to-back bipolar junctions.

Abstract: A probe card for testing or trimming or programming a semiconductor wafer including a first die including a first integrated circuit having a trimmable or programmable component. The probe card including at least one probe arranged to make electrical contact with at least one probe pad arranged on the wafer. The at least one probe pad being electrically connected to the trimmable or programmable component and being arranged in a saw street of the wafer.

Abstract: A semiconductor device includes a first top selection structure and a second top selection structure at a same vertical level as and separated from a main signal pad, and respectively extending along different directions; a first ground layer at the same vertical level as and separated from the main signal pad and the top selection structures; a first bottom selection structure at a vertical level lower than the main signal pad and partially overlapped with the top selection structures and the first ground layer in a top-view perspective; a first top via between the first ground layer and the first bottom selection structure; second top vias between the top selection structures and the first bottom selection structure; first insulating layers between the second top vias and the first bottom selection structure; and a wiring pad on the main signal pad and the top selection structures.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

Abstract: An electronic device includes a substrate, a support body, and a conductive film. The substrate is a piezoelectric substrate or a compound semiconductor substrate including a first main surface with functional elements. The support body is provided at a second main surface of the substrate opposite to the first main surface and has a higher thermal conductivity than the substrate. The conductive film is located in a through hole extending through the support body and has a higher thermal conductivity than the support body.