Abstract: A method of fabricating a device includes providing a substrate of the device, forming a structure of the device, the structure being supported by the substrate, having a semiconductor composition, and including a surface, where nitrogen is present at the surface, and incorporating oxygen into the surface to form a stabilizing layer on the surface.

Abstract: A micro-LED chip includes an epitaxial structure, which includes first and second doped type semiconductor layers and an active layer disposed between the first and second doped type semiconductor layers; a light-emitting side of the first doped type semiconductor layer facing away from the active layer is provided with a patterned structure; and an elongated edge a of the micro-LED chip, a thickness b of the micro-LED chip, and a peak-valley height difference c of the patterned structure satisfy: 0.01?b/a?6, and 0.01?c/b?0.3. By designing a structure size and/or a shape of the micro-LED chip combined with designing the peak-valley height difference of the patterned structure to satisfy the condition of 0.01?c/b?0.3, power of laser lift-off operation can be reduced and a process window thereof is enlarged, and light extraction efficiency of the micro-LED chip is achieved. And a display device using the micro-LED chip is provided.

Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

Abstract: An organic light emitting display apparatus includes a plurality of pixels on a substrate, each including a plurality of subpixels each including an emission area, a planarization layer including a light extraction pattern which is at the emission area of each of the plurality of subpixels and includes a plurality of concave portions, and a light emitting device layer on the light extraction pattern. One or more of the plurality of subpixels comprise a plurality of pattern regions, and the light extraction pattern at each of the plurality of pattern regions comprises a structure which has rotated with respect to a reference point.

Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a first gate structure disposed over a substrate in an active device region, an insulating material disposed over the substrate in a passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, a second conductive contact disposed over the resistor structure, and a dielectric layer in contact with the second conductive contact and the resistor structure.

Abstract: A semiconductor wafer comprising a first die including a first integrated circuit having a trimmable or programmable component. The trimmable or programmable component is configured to be trimmed or permanently altered in response to an electrical signal. The semiconductor wafer includes a second die arranged adjacent to the first die. The second die includes a second integrated circuit and at least one contact pad arranged to allow an electrical connection to be made to the second integrated circuit. The at least one contact pad is additionally electrically connected to the at least one trimmable or programmable component of the first die such that the at least one contact pad of the second die is configured to act as a probe pad.

Abstract: A semiconductor device includes a switching element, and a data storage structure electrically connected to the switching element. The data storage structure includes first electrodes, a second electrode, and a dielectric layer between the first electrodes and the second electrode. The second electrode includes a compound semiconductor layer doped with an impurity element, the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element, the two or more elements include a first element and a second element, the first element is silicon (Si), and a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %.

Abstract: Disclosed systems and techniques are directed to mitigating stresses in substrate-to-substrate bonding processes. Disclosed techniques include obtaining a first substrate supporting transferred feature(s) (TFs) and transferring TFs from the first substrate to a second substrate, transferring TFs from the first substrate to the second substrate, and applying stress mitigation to a target substrate. The target substrate can be the first substrate, an auxiliary substrate supporting TFs prior to transferring TFs from the auxiliary substrate to the first substrate, or the second substrate. Applying stress mitigation to the target substrate includes obtaining an out-of-plane deformation (OPD) profile of the target substrate, causing a stress compensation layer (SCL) to be deposited on the target substrate, and exposing the SCL to a stress-mitigation beam. Settings of the SCL and/or the stress-mitigation beam are determined using the OPD profile of the target substrate.

Abstract: Disclosed in embodiments of the present application are a linear resistive element and a preparation method therefor. The linear resistive element includes a substrate unit, a function unit and an electrode unit. The substrate unit includes a substrate layer, which is configured to connect the function unit and the electrode unit. The electrode unit includes a first electrode and a second electrode. The first and second electrodes are deposited on the substrate layer, and the function unit is connected between the first and second electrodes. The function unit includes first dielectric layers and resistive layers. The first dielectric layers and the resistive layers are deposited on the substrate layer in an alternately stacked manner. A number of the resistive layers is at least two, and a conductive filament for conductively connecting the first and second electrodes is formed in each of the resistive layers.

Abstract: Provided is a semiconductor device having high heat dissipation and high operation reliability. This semiconductor device includes a semiconductor substrate, a first semiconductor layer that is provided on the semiconductor substrate, has a first aperture, and has a first thermal conductivity, a transistor (Tr) provided on the first semiconductor layer, and a heat dissipation unit that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.

Abstract: A semiconductor device includes a semiconductor substrate, a first electroconductive member that is formed on the semiconductor substrate and that has a first linear portion extending along a principal surface of the semiconductor substrate, and an organic insulation layer that is formed on the semiconductor substrate and that covers the first electroconductive member, and the first linear portion includes a first side edge portion formed by a curve that is alternately bent to one side and to an opposite side of a direction intersecting a longitudinal direction of the first linear portion in a plan view.

Abstract: Provided is a semiconductor device including a semiconductor substrate, a gate stack including a plurality of gate layers and a plurality of insulation layers alternately stacked on the semiconductor substrate, a plurality of first channel structures penetrating through the gate stack and extending in a vertical direction, a word line cut penetrating through the gate stack and extending in the vertical direction, a passivation layer disposed on the gate stack, and a string select line stack disposed on the passivation layer, wherein the passivation layer includes a first passivation layer containing a passivation element and a second passivation layer having a smaller content of the passivation element than the first passivation layer.

Abstract: A high-voltage semiconductor device which has a substrate, a gate field plate, a gate region, and a drift region and a method of manufacturing the high-voltage semiconductor device are described. The drift region has a first impurity region and a second impurity region covering at least one side wall of the first impurity region. The high-voltage semiconductor device is capable of alleviating electric field concentration at an edge of a gate field plate and of preventing deterioration of characteristics of specific on-resistance (Rsp) by having a second impurity region in the drift region covering the first impurity region.

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

Abstract: In a silicon carbide semiconductor device, in a plan view, a plurality of source contact holes is intermittently provided in a second direction along a trench gate, and a source electrode is provided on an insulating film and is electrically connected to a source layer via the plurality of source contact holes. Intermittent recesses reflecting the shapes of the plurality of source contact holes are provided on a surface of the source electrode on a side opposite to the semiconductor substrate.

Abstract: A fuse element including a first bimetallic pillar disposed between and electrically connecting a first metal level to a second metal level, the first bimetallic pillar comprises a first metal strip adjacent to a second metal strip. A fuse element including a first bimetallic pillar disposed between and electrically connecting a first metal level to a second metal level, the first bimetallic pillar includes a first metal strip adjacent to a second metal strip, a first width of the second metal strip is substantially equal to a width of the bimetallic pillar. A fuse element including a first bimetallic pillar disposed between and electrically connecting a first metal level to a second metal level, the first bimetallic pillar includes a first metal strip adjacent to a second metal strip, the second metal strip is physically disposed between a bottom surface of the first metal strip and the first metal level.

Abstract: A display device includes a substrate having a first pixel area, a second pixel area offset from the first pixel area, a third pixel area offset from the second pixel area and a fourth pixel area offset from the third pixel area, and having a first sub valley area between the first pixel area and the second pixel area, a second sub valley area between the third pixel area and the fourth pixel area, and a main valley area between the second pixel area and the third pixel area; an inorganic insulating layer on the substrate and defining a first groove, a third groove, and a second groove respectively overlapping the first sub valley area, the second sub valley area, and the main valley area; and an organic insulating layer on the inorganic insulating layer and filling the first groove, the second groove and the third groove.

Abstract: A display device includes a substrate having first and second surfaces, transistors, data lines, and light-emitting diodes above the first surface, front data pads above the first surface, electrically connected to the data lines, and arranged in a first direction along a first side of the substrate, a first insulating layer above the front data pads, rear data pads under the second surface, and arranged in the first direction, a second insulating layer under the rear data pads, and defining first and second openings overlapping one of the rear data pads, a first virtual line extending from the first opening in the first direction not overlapping the second opening, and a side wire connecting a front data pad to a rear data pad, and electrically connected to and overlapping the first rear data pad through the first opening.

Abstract: Disclosed herein are microelectronic assemblies with direct bonding using nanotwinned copper (NTC). An example microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding (DB) region, wherein the DB region includes a DB contact comprising a first portion and a second portion having different microstructures. The first portion is between the first microelectronic component and the second portion. The second portion is between the first portion and the second microelectronic component. In some implementations, the first portion has non-columnar microstructure, and the second portion has columnar microstructure. In some implementations, less than about 40% of grains of the first portion have ac <111> orientation, and at least about 50% of grains of the second portion have the <111> orientation.

Abstract: A display device includes an interlayer insulating layer exposing an auxiliary line, a protection layer disposed on the interlayer insulating layer and removed from an area above the auxiliary line, a pixel defining layer disposed on the protection layer and including a first portion covering one side surfaces of the protection layer and the interlayer insulating layer and a second portion protruding toward the first portion beyond an edge of other side surfaces of the interlayer insulating layer and the protection layer and defining a undercut area, a light emitting layer covering the first portion of the pixel defining layer and exposing the auxiliary line in the undercut area, and a cathode electrode disposed on the light emitting layer and contacting the auxiliary line in the undercut area.