Abstract: A semiconductor device includes a bit line extending in a first direction on a substrate. A first insulating pattern is disposed on the bit line. A channel pattern is disposed on an upper side of the bit line and a lateral side of the first insulating pattern. The channel pattern includes an oxide semiconductor material. A gate insulating pattern is disposed on the channel pattern. Word lines are disposed on the gate insulating pattern. A second insulating pattern is disposed on the word lines. A landing pad is disposed on the channel pattern. An interlayer insulating layer disposed between the bit line and the channel pattern.

Abstract: [Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin. [Solution] A semiconductor module 1 includes semiconductor chips 14a to 14d, sealing resin 18 configured to seal the semiconductor chips 14a to 14d, a case 11 including a casting area 117u, first portions 111 and 112, and second portions 113 and 114, wire wirings 101a to 101j and 102a to 102i sealed in the sealing resin 18 while being located closer to the first portion 111 and connected to the semiconductor chips 14a to 14d, and recessed portions 131a, 131b, 132a, and 132b formed on the second portions 113 and 114 between a virtual surface VSu and the first portion 112.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures. The integrated circuit structure also includes a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures. The second pitch is greater than the first pitch.

Abstract: A display device comprises a substrate, a sub-pixel disposed on the substrate and that includes a pixel electrode, a light emitting layer, and a common electrode, a pixel defining layer that defines the sub-pixel, a capping layer disposed on the pixel defining layer, a micro lens disposed on the capping layer and that overlaps the sub-pixel; and a total reflection pattern disposed on the capping layer and that overlaps the pixel defining layer and surrounds the micro lens. The micro lens has a refractive index greater than a refractive index of the total reflection pattern and less than or equal to a refractive index of the capping layer.

Abstract: A method for manufacturing a semiconductor element includes preparing a semiconductor wafer that includes a substrate including a Ga2O3-based semiconductor and an epitaxial layer including a Ga2O3-based semiconductor and located on the substrate, fixing the epitaxial layer side of the semiconductor wafer to a support substrate, thinning the substrate of the semiconductor wafer fixed to the support substrate, after the thinning of the substrate, forming an electrode on a lower surface of the substrate, bonding or forming a support metal layer on a lower surface of the electrode of the semiconductor wafer, and dicing the semiconductor wafer into individual pieces, thereby obtaining plural semiconductor elements each including the support metal layer. Thermal conductivity of the support metal layer is higher than thermal conductivity of the substrate.

Abstract: A diamond-based particle detector includes a diamond substrate that includes a first side and a second side; a first side first doped layer contacting the first side of the diamond substrate; a first metal contact contacting the first side first doped layer, a first side intrinsic diamond layer contacting the first side first doped layer, (i) a second side first doped layer or (ii) a second side intrinsic diamond layer contacting the second side of the diamond substrate; and a second metal contact contacting (i) the second side first doped layer or (ii) the second side intrinsic diamond layer.

Abstract: Disclosed is a semiconductor structure. The semiconductor structure includes a support structure, and a first dielectric layer and a growth substrate sequentially formed on the support structure, where a gravity center of the support structure and a gravity center of the growth substrate are disposed in a staggered manner, so that the direct contact between the growth substrate and the graphite disk can be avoided, a centrifugal force on the growth substrate exerted by the graphite disk to the support structure can be transferred, thereby further ensuring a quality of the growth substrate, and significantly reducing a probability of cracking to ensure a crystal quality of a subsequent epitaxial layer. The support structure is formed at the bottom of the growth substrate, so that a mechanical strength of the semiconductor structure can be effectively improved, a stability can be enhanced, and a deformation of the semiconductor structure can be suppressed.

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

Abstract: A display device includes a first conductive layer; a first insulating layer on the first conductive layer; a semiconductor layer disposed on the first insulating layer and electrically connected to the first conductive layer; a second conductive layer disposed on the semiconductor layer and electrically connected to the first conductive layer; and light emitting elements on the second conductive layer. A thickness of a part of the first insulating layer in a first area, which overlaps the semiconductor layer in a plan view, is different from a thickness of another part of the first insulating layer in a second area, which is exposed by the semiconductor layer.

Abstract: A thermal management system includes a baseplate assembly and a flow system. The baseplate assembly includes a baseplate and a semiconductor die. The flow system includes a submerged jet impingement assembly for direct semiconductor die cooling, a first flow path extending over the semiconductor die via the submerged jet impingement assembly, and a second flow path in thermal contact with the baseplate, the flow system including a fluid flowing through the first flow path and the second flow path. The flow system is configured to direct the fluid to the upper semiconductor surface of the semiconductor die via the first flow path and to the baseplate via the second flow path so as to transfer heat away from the semiconductor die and from the baseplate so as to cool the baseplate assembly.

Abstract: An infrared light emitter includes a substrate, a first light-emitting layer, a blocking layer, and a second light-emitting layer. The second light-emitting layer is disposed on the substrate, the blocking layer is disposed on the second light-emitting layer, and the first light-emitting layer is disposed on the blocking layer. The first light-emitting layer, the blocking, and the second light-emitting layer form a P-N-P junction or an N-P-N junction. The first light-emitting layer and the blocking layer form a first electroluminescent unit, and the blocking layer and the second light-emitting layer form a second electroluminescent unit. The first electroluminescent unit and the second electroluminescent unit build two back-to-back bipolar junctions.

Abstract: A probe card for testing or trimming or programming a semiconductor wafer including a first die including a first integrated circuit having a trimmable or programmable component. The probe card including at least one probe arranged to make electrical contact with at least one probe pad arranged on the wafer. The at least one probe pad being electrically connected to the trimmable or programmable component and being arranged in a saw street of the wafer.

Abstract: A semiconductor device includes a first top selection structure and a second top selection structure at a same vertical level as and separated from a main signal pad, and respectively extending along different directions; a first ground layer at the same vertical level as and separated from the main signal pad and the top selection structures; a first bottom selection structure at a vertical level lower than the main signal pad and partially overlapped with the top selection structures and the first ground layer in a top-view perspective; a first top via between the first ground layer and the first bottom selection structure; second top vias between the top selection structures and the first bottom selection structure; first insulating layers between the second top vias and the first bottom selection structure; and a wiring pad on the main signal pad and the top selection structures.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

Abstract: An electronic device includes a substrate, a support body, and a conductive film. The substrate is a piezoelectric substrate or a compound semiconductor substrate including a first main surface with functional elements. The support body is provided at a second main surface of the substrate opposite to the first main surface and has a higher thermal conductivity than the substrate. The conductive film is located in a through hole extending through the support body and has a higher thermal conductivity than the support body.

Abstract: A direct cooling type power module comprising, an enclosure filled with an insulating fluid, a power semiconductor device disposed inside the enclosure and a bonding unit comprising a porous layer, and a thermally conductive layer to which the power semiconductor device is bonded, and allowing the power semiconductor device to exchange heat with the insulating fluid by the porous layer and the thermally conductive layer.

Abstract: A microelectromechanical system (MEMS) switch implemented with a coplanar waveguide. The MEMS switch includes an input terminal, an output terminal. The MEMS switch includes a beam extending between the input terminal and the output terminal. The beam includes a first edge and a second edge coupled to a gate of the MEMS switch. The beam includes a third edge proximate the input terminal. The first edge includes a first set of finger contacts proximate a first corner of the beam and a second set of finger contacts proximate a second corner of the beam. The beam includes a fourth edge proximate the output terminal, the fourth edge opposing the third edge. The MEMS switch has a first anchor coupled to the input terminal. The first anchor includes a first segment extending from a region proximate the input terminal to a region overlying the first set of finger contacts.

Abstract: A package structure is provided. The package structure has a light-emitting region and a non-light-emitting region that is adjacent to the light-emitting region, and includes a substrate, a first light-emitting layer, a second light-emitting layer and a third light-emitting layer. The first light-emitting layer, the second light-emitting layer and the third light-emitting layer are sequentially stacked on the substrate. Each of the first light-emitting layer, the second light-emitting layer and the third light-emitting layer includes a transparent adhesive layer disposed in the light-emitting region, a light-emitting diode (LED) chip disposed on the transparent adhesive layer, a redistribution layer formed on the LED chip and extending from the light-emitting region to the non-light-emitting region, and a planarization layer disposed on the LED chip and the redistribution layer.

Abstract: According to one embodiment, a semiconductor memory device includes a first wiring layer above a first semiconductor layer in a first direction and a second wiring layer above the first semiconductor layer and spaced from the first wiring layer in a second direction. A first memory pillar extends through the first wiring layer. A second memory pillar extends through the second wiring layer. A member is between the first and second wiring layers in the second direction and includes a first conductor contacting the first semiconductor layer, a first insulator between the wiring layers and the first conductor, and a plurality of second insulators arranged along a third direction and between the first conductor and the first semiconductor layer in the first direction.

Abstract: A semiconductor device includes a gate electrode structure, a first division pattern, and a memory channel structure. The gate electrode structure includes gate electrodes stacked in a first direction and extending in a second direction. The first division pattern extends in the second direction through the gate electrode structure, and divides the gate electrode structure in a third direction. The memory channel structure extends through the gate electrode structure, and includes a channel and a charge storage structure. The first division pattern includes first and second sidewalls opposite to each other in the third direction. First recesses are spaced apart from each other in the second direction on the first sidewall, and second recesses are spaced apart from each other in the second direction on the second sidewall. The first and second recesses do not overlap in the third direction.