Patents Examined by Evren Seven
  • Patent number: 10691019
    Abstract: A pattern-forming method includes forming a base pattern having recessed portions on a front face side of a substrate directly or via other layer. The recessed portions of the base pattern are filled with a first composition to form a filler layer. Phase separation of the filler layer is allowed to form a plurality of phases of the filler layer. A part of the plurality of phases of the filler layer is removed to form a miniaturized pattern. The forming of the base pattern includes: forming a resist pattern on the front face side of the substrate; forming a layer of a second polymer on lateral faces of the resist pattern; and forming a layer of a third polymer that differs from the second polymer on a surface of the substrate or on a surface of the other layer.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: June 23, 2020
    Assignee: JSR CORPORATION
    Inventors: Hiroyuki Komatsu, Takehiko Naruoka, Masafumi Hori, Hitoshi Osaki, Tomohiro Oda
  • Patent number: 10686010
    Abstract: In fabricating a semiconductor device, a shared material is formed in a resonator region of the semiconductor device and in a phase-change material (PCM) switch region of the semiconductor device. A portion of the shared material is removed to concurrently form a heat spreader comprising the shared material in the PCM switch region and a piezoelectric segment comprising the shared material in the resonator region. The piezoelectric segment in the resonator region and the heat spreader in the PCM switch region are situated at substantially the same level in the semiconductor device. The PCM switch region includes a heating element between the heat spreader and a PCM. The resonator region includes the piezoelectric segment between two electrodes.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 16, 2020
    Assignee: Newport Fab, LLC
    Inventors: Gregory P. Slovin, Nabil El-Hinnawy, Jefferson E. Rose, David J. Howard
  • Patent number: 10679719
    Abstract: A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design circuitry which, when activated, repairs the particular transistor by self-heating. The method can comprise determining a memory cell that has a read current below a passing criteria, the memory cell having a transistor with a nanowire channel on a current path through which the read current flows; and applying a stress on the memory cell to repair the nanowire channel of the transistor in the memory cell on the current path. The determining step can include sensing read currents of memory cells in an array of memory cells; and determining one or more memory cells in the array of memory cells having read currents below the passing criteria, using the read currents sensed.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 9, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Jamil Kawa, Victor Moroz
  • Patent number: 10672924
    Abstract: Laser foil trim approaches for foil-based metallization of solar cells, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes attaching a metal foil sheet to a surface of a wafer to provide a unified pairing of the metal foil sheet and the wafer, wherein the wafer has a perimeter and the metal foil sheet has a portion overhanging the perimeter. The method also includes laser scribing the metal foil sheet along the perimeter of the wafer using a laser beam that overlaps the metal foil sheet outside of the perimeter of the wafer and at the same time overlaps a portion of the unified pairing of the metal foil sheet and the wafer inside the perimeter of the wafer to remove the portion of the metal foil sheet overhanging the perimeter and to provide a metal foil piece coupled to the surface of the wafer.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: June 2, 2020
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Robert Woehl, Richard Hamilton Sewell, Mohamed A. Elbandrawy, Taeseok Kim, Thomas P. Pass, Benjamin Ian Hsia, David Fredric Joel Kavulak, Nils-Peter Harder
  • Patent number: 10672758
    Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 2, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Vadim Valentinovic Vendt, Stefan Pompl, Andre Schmenn, Joost Willemen
  • Patent number: 10665320
    Abstract: A method for improving an integrated circuit design having transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating. A critical path in logic circuitry in the design can be determined including a particular device having a transistor with a nanowire channel. A repair circuit can be added to the design connected to the particular device, the repair circuit when activated applying a self-heating stress to the particular device. The repair circuit can include a selection block selecting among a plurality of signals as an input signal to the particular device. The plurality of signals include a repair signal and an operational logic signal, the repair signal being such as to apply the self-heating stress to the nanowire channel of the particular device when activated.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 26, 2020
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Victor Moroz
  • Patent number: 10651181
    Abstract: The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO2 layer that surrounds side surfaces of a P+ layer 38a and N+ layers 38b and 8c formed on a Si pillar 6b by epitaxial crystal growth, forming an AlO layer 51 on a periphery of the SiO2 layer, forming a tubular contact hole by etching the tubular SiO2 layer using the AlO layer 51 as a mask, and filling the contact hole with W layers 52c, 52d, and 52e to form tubular W layers 52c, 52d, and 52e (including a buffer conductor layer) that have an equal width when viewed in plan and are in contact with side surfaces of the tops of the P+ layer 38a and the N+ layers 38b and 8c.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: May 12, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Phillipe Matagne, Yoshiaki Kikuchi
  • Patent number: 10649447
    Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: May 12, 2020
    Assignee: KLA-Tencor Corp.
    Inventors: Pavel Izikson, John Robinson, Mike Adel, Amir Widmann, Dongsub Choi, Anat Marchelli
  • Patent number: 10643844
    Abstract: Provided herein is a method for manufacturing a semiconductor device. The method may include: forming a stack including at least one first material layer and at least one second material layer which are alternately stacked; forming first holes through which the at least one first material layer is exposed; forming etch stop patterns in the respective first holes; forming at least one slit passing through the stack; replacing the at least one first material layer with at least one third material layer through the at least one slit; and forming first contact plugs in the respective first holes, the first contact plugs passing through the etch stop patterns and coupled with the at least one third material layer.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10636876
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to devices with channel extension regions and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; and a channel below the gate structure, the channel comprising: a first channel region, adjacent to the source region; and a second channel region, adjacent to the drain region and comprising a lower threshold voltage than the first channel region.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lars Müller-Meskamp, Luca Pirro, Edward J. Nowak
  • Patent number: 10629798
    Abstract: In-situ patterning of semiconductor structures is performed using one or more “shadow walls” in conjunction with an angled deposition beam. A shadow wall protrudes outwardly from the surface of a substrate to define an adjacent shadow region in which deposition is prevented due to the shadow wall inhibiting the passage of the angled deposition beam. Hence, deposition will not occur on a surface portion of a semiconductor structure within the shadow region. Shadow walls can thus be used to achieve selective patterning of semiconductor structures. The shadow walls themselves are formed of semiconductor. In one implementation, the semiconductor structure and the one or more shadow walls used to selectively pattern it may be formed using selective area growth (SAG).
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: April 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Raymond Leonard Kallaher, Geoffrey Charles Gardner, Sergei Vyacheslavovich Gronin
  • Patent number: 10622265
    Abstract: A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Young Choi, Zhan Zhan, Min-Seob Kim, Ju-Hyun Kim, Sung-Gun Kang, Hwa-Sung Rhee
  • Patent number: 10622560
    Abstract: A semiconductor chip or system, such as a multi-chip module (MCM), a system-in-package (SiP), and/or a printed circuit board (PCB) module, includes a substrate, a resonator and/or a micro-electrical-mechanical system (MEMS), and a phase-change material (PCM) switch. The PCM switch includes a hearing element, a PCM situated over the heating element, and PCM contacts connected to passive segments of the PCM. The heating element is transverse to the PCM and approximately defines an active segment of the PCM. The PCM contacts are electrically connected to the resonator and/or the MEMS in a shared routing region of the semiconductor chip. The PCM switch is configured to engage or disengage the resonator and/or the MEMS. In one approach, a plurality of PCM switches are capable of reconfiguring an array of resonators and/or an array of MEMS. In another approach, a redundant PCM switch is electrically connected to a redundant resonator and/or a redundant MEMS.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 14, 2020
    Assignee: Newport Fab, LLC
    Inventors: David J. Howard, Nabil El-Hinnawy
  • Patent number: 10615175
    Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong Sung Jeon, Eun Mee Kwon, Da Som Lee, Bong Hoon Lee
  • Patent number: 10615305
    Abstract: Embodiments relate to a method for fabricating a light-emitting-diode (LED). A metal layer is deposited on a p-type semiconductor. The p-type semiconductor is on an n-type semiconductor. The metal layer is patterned to define a p-metal. The p-type semiconductor is etched using the p-metal as an etch mask. Similarly, the n-type semiconductor is etched using the p-metal and the p-type semiconductor as an etch mask to define individual LEDs.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: April 7, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Celine Claire Oyer, Allan Pourchet
  • Patent number: 10615290
    Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10613157
    Abstract: Certain embodiments may generally relate to a smart fault detection device for power grids, and a method of fault detection for power grids. A method may include receiving raw data samples of currents in grounding conductors and line conductors. The method may also include processing the raw data samples under at least one of a plurality of system operating modes. The method may also include monitoring normal operation and anticipating an impending fault while operating under at least one of the system operating modes. The method may further include extracting fault information based on the monitoring. The method may also include reporting the fault information to a supervisory control and data acquisition system human-machine interface. The method may further include anticipating faults based on an analysis of the raw data samples.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 7, 2020
    Assignees: QATAR UNIVERSITY, UNIVERSITY OF WATERLOO, UNITED ARAB EMIRATES UNIVERSITY
    Inventors: Ahmed Gaouda, Khaled Bashir Shaban, Magdy Salama, Atef Abdrabou, Ramadan Elshatshat, Mutaz Mohamed Elhassan Elsawi Khairalla, Ahmed Abdrabou
  • Patent number: 10608407
    Abstract: A method of manufacturing a semiconductor laser element includes: a cleaning process of holding a semiconductor light emission element that emits light from a facet thereof in a plasma sputtering device in which a target is covered with quartz, and cleaning the facet by irradiating the facet with plasma in the plasma sputtering device; and a dielectric film formation process of transporting the cleaned semiconductor light emission element to a deposition device without exposing the semiconductor light emission element to an atmosphere, and forming a dielectric film on the cleaned facet in the deposition device.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 31, 2020
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yutaka Ohki, Masafumi Tajima
  • Patent number: 10607846
    Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 31, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidehiko Karasaki, Noriyuki Matsubara, Atsushi Harikai, Hidefumi Saeki
  • Patent number: 10597768
    Abstract: There are provided a vapor deposition mask capable of satisfying both high definition and lightweight in upsizing and forming a vapor deposition pattern with high definition while securing strength, a vapor deposition mask preparation body capable of simply producing the vapor deposition mask and a method for producing a vapor deposition mask, and furthermore, a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition. A metal mask 10 in which a slit 15 is provided and a resin mask 20 in which openings 25 corresponding to a pattern to be produced by vapor deposition are provided at a position of overlapping with the slit 15 are stacked, and the metal mask 10 has a general region 10a in which the slit 15 is provided and a thick region 10b larger in thickness than the general region.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: March 24, 2020
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsunari Obata, Toshihiko Takeda, Hiroshi Kawasaki, Hiroyuki Nishimura, Atsushi Maki, Hiromitsu Ochiai, Yoshinori Hirobe