Abstract: A display device includes an interlayer insulating layer exposing an auxiliary line, a protection layer disposed on the interlayer insulating layer and removed from an area above the auxiliary line, a pixel defining layer disposed on the protection layer and including a first portion covering one side surfaces of the protection layer and the interlayer insulating layer and a second portion protruding toward the first portion beyond an edge of other side surfaces of the interlayer insulating layer and the protection layer and defining a undercut area, a light emitting layer covering the first portion of the pixel defining layer and exposing the auxiliary line in the undercut area, and a cathode electrode disposed on the light emitting layer and contacting the auxiliary line in the undercut area.

Abstract: Provided is a semiconductor device. A semiconductor device is implemented as a semiconductor module package for driving an inverter, the semiconductor device may include: a first upper metal layer in which a plurality of semiconductor chips implementing a right phase switching pattern are disposed along a first direction to form a first row; a second upper metal layer in which a plurality of semiconductor chips implementing a left phase switching pattern are disposed along the first direction to form a second row; a first connection, in the first upper metal layer, connecting a plurality of semiconductor chips disposed along the first row to each other in series and to the second upper metal layer in parallel; and a second connection, in the second upper metal layer, connecting a plurality of semiconductor chips disposed along the second row to each other in series.

Abstract: A package includes a semiconductor die disposed on a three-layer substrate. The three-layer substrate includes a ceramic layer disposed between a top metal layer and a bottom metal layer. The semiconductor die is disposed on the top metal layer. An array of mesas is defined in the bottom metal layer with grooves between the mesas forming a path for cooling fluid flow across a surface of the bottom metal layer.

Abstract: Some embodiments include apparatuses in which one of the apparatuses includes a first conductive structure, a second conductive structure, a third conductive structure, and a memory cell. The memory cell includes a semiconductor portion located on a first level of the apparatus and coupled to the first conductive structure, and a charge storage structure located on the first level coupled to the semiconductor portion and separated from the second conductive structure. The third conductive structure is located on a second level of the apparatus adjacent the semiconductor portion, and including first, second, and third conductive regions. The third conductive region is located between the first and second conductive regions and has a material different from a material of the first conductive region and a material of the second conductive region.

Abstract: A method for reducing warpage occurred to a substrate during a packaging process includes attaching a plurality of dies to an upper surface of the substrate; attaching an adhesive material having a first curing temperature to a lower surface of the substrate; applying a liquid-packaging material having a second curing temperature to surroundings of the dies; heating the substrate, the adhesive material, and the liquid-packaging material to a heating temperature not less than the first curing temperature and the second curing temperature; and cooling the substrate, the adhesive material, and the liquid-packaging material to a room temperature. When being cooled to the room temperature, the liquid-packaging material applies an upper-surface shrinkage stress to the upper surface of the substrate, the adhesive material applies a lower-surface shrinkage stress to the lower surface of the substrate, and the lower-surface shrinkage stress is substantially equal to the upper-surface shrinkage stress.

Abstract: A semiconductor integrated circuit (IC) device includes a diffusion break region that has a diffusion break dielectric adjacent to or between diffusion break isolation wall(s). The diffusion break region may separate adjacent transistors. The diffusion break isolation wall(s) may include respective retained portions of a backside spacer, a bottom isolation, respective inner spacers, and residual active semiconductor nanolayers. The diffusion break region may be fabricated by depositing a diffusion break dielectric within a diffusion break opening against the diffusion break isolation wall(s).

Abstract: According to one embodiment, a manufacturing method includes preparing a substrate including panel portions and a margin area, forming lower electrodes, forming a rib, forming a first partition in the margin area, forming a first stacked film, and forming a first sealing layer. The first stacked film is formed in an entire of the substrate and is divided into portions by the first partition. The first sealing layer continuously covers these portions. An end portion of the substrate is spaced apart from an end portion of the first sealing layer. The first stacked film is exposed from the first sealing layer in an area between the end portions of the substrate and the first sealing layer.

Abstract: Embodiments disclosed herein include semiconductor die with overlay marks, electronic devices that include semiconductor dies with overlay marks, and methods of measuring overlay. In one embodiment, a semiconductor die includes multiple overlay marks, including a first overlay mark and a second overlay mark. The first overlay mark is at a first position on the semiconductor die and includes a first set of patterns with a first orientation. The second overlay mark is at a second position on the semiconductor die and includes a second set of patterns with a second orientation. The first position of the first mark and the second position of the second mark are non-overlapping. In addition, the first orientation of the patterns in the first mark is substantially orthogonal to the second orientation of the patterns in the second mark.

Abstract: A display device includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a common voltage line disposed in the display area and connected to the external common voltage line; a plurality of pixels positioned in the display area, each of which includes a first electrode and an emission layer; and a second electrode positioned on the pixels. The common voltage line has a multi-layered structure including a first layer, a second layer, and a third layer, the second layer defines an undercut structure therein, a width of the second layer is narrower than a width of each of the first layer and the third layer, and a length of an undercut of the undercut structure is greater than a thickness of the common voltage line.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer, a test structure, and a photoresist pattern. The semiconductor wafer has a substrate with die areas separated by a scribe line area. The test structure disposed in the scribe line area includes first and second transistor test units. The photoresist pattern is arranged between the first and second transistor test units. The first gate structures of the first and second transistor test units are electrically connected to each other. The second gate structures of the first and second transistor test units are electrically connected to each other. A first drain region of the first transistor test unit is electrically connected to a first source region of the second transistor test unit. A second drain region of the first transistor test unit is electrically connected to a second source region of the second transistor test unit.

Abstract: Coupling qubits is provided. The method comprises embedding a tin atom in a silicon substrate and forming a number of quantum dot electrodes over the silicon substrate. The quantum dot electrodes draw an electron from an electron source into the silicon substrate and performing an electron-nuclear controlled-phase gate operation by: moving the electron adiabatically toward the tin atom to achieve a specified level of hyperfine interaction (HFI) between the electron and the nucleus of the tin atom to minimize the effect of noise; holding the electron at the distance of the specified HIFI for a specified duration of time to represent an “on” state; and moving the electron adiabatically away from the tin atom to lower the HFI below the specified level and represent an “off” state.

Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a fin structure over a substrate, forming an insulating material adjacent the fin structure, depositing a gate dielectric layer over the fin structure and the insulating material, depositing a gate electrode layer on the gate dielectric layer, forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material, then performing an etch process that etches the gate dielectric layer at a faster rate than the gate electrode layer, and filling the opening with a dielectric material.

Abstract: A device includes an antifuse structure. The antifuse structure includes a first contact structure and a second contact structure in a first interlevel dielectric (ILD) layer, an opening arranged between the first contact structure and the second contact structure in the first ILD layer, and a dielectric capping layer lining at least sidewalls of the opening. A second ILD layer is arranged over the first ILD layer and in the opening. The second ILD layer lines the dielectric capping layer on at least the sidewalls of the opening. A third contact structure is arranged between the first contact structure and the second contact structure. The third contact structure includes a first portion in the opening.

Abstract: A semiconductor device includes a semiconductor body having first and second opposite surfaces along a vertical direction, and an active diode area. The active diode area includes: a p-doped anode region adjoining the first surface; an n-doped drift region between the anode region and the second surface; an n-doped cathode contact region adjoining the second surface; a p-doped injection region adjoining the second surface and the cathode contact region; and a p-doped auxiliary region between the drift region and the cathode contact region. The auxiliary region includes first and second sub-regions. In a top view, the first sub-region covers at least part of the injection region and the second sub-region covers at least part of the cathode contact region. In the top view, the auxiliary region includes a plurality of openings covering from 0.1% to an 20% of a surface area of the active diode area at the second surface.

Abstract: A semiconductor device that can be subjected to multipoint measurement is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a first multiplexer, a second multiplexer, m (m is an integer of 1 or more) analog switches electrically connected to the first multiplexer, and n (n is an integer of 1 or more) analog switches electrically connected to the second multiplexer. The second layer includes m×n transistors. Each of the m analog switches is electrically connected to n transistors, and each of the n analog switches is electrically connected to m transistors.

Abstract: A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.

Abstract: A display device includes a trench, which includes: first and second trench lines respectively located between neighboring column lines and between neighboring row lines, wherein the first trench line includes a first side groove in a column direction, and first and second corner grooves connected between adjacent first side grooves, forming an isosceles portion protruding to one side in a row direction, having second and first diagonal directions, respectively, and connected to each other at a first contact point, wherein the second trench line includes a second side groove in the row direction, and the first and second corner grooves connected between adjacent second side grooves, forming an isosceles portion protruding to one side in the column direction, and connected to each other at a second contact point, wherein the protruding isosceles portions of the first and second trench lines share the first corner groove.

Abstract: An input feedthrough (8) and an output feedthrough (9) provided on the substrate (3) are wire-connected to an input pad (5) and an output pad (6) of the semiconductor chip (4) respectively. A metal seal ring (12) is provided on the substrate (3) is electrically connected to the metal plate (1) by a through-hole (15). A conductive cap (14) is bonded to the metal seal ring (12) and covers a place above the semiconductor chip (4). Both ends of an isolation metal wire (13) are electrically connected to the metal plate (1) and a loop comes into contact with a lower surface of the conductive cap (14). The isolation metal wire (13) constitutes an isolation wall partitioning an inner space into a region including the input feedthrough (8) and a region including the output feedthrough (9).

Abstract: [Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin. [Solution] A semiconductor module 1 includes semiconductor chips 14a to 14d, sealing resin 18 configured to seal the semiconductor chips 14a to 14d, a case 11 including a casting area 117u, first portions 111 and 112, and second portions 113 and 114, wire wirings 101a to 101j and 102a to 102i sealed in the sealing resin 18 while being located closer to the first portion 111 and connected to the semiconductor chips 14a to 14d, and recessed portions 131a, 131b, 132a, and 132b formed on the second portions 113 and 114 between a virtual surface VSu and the first portion 112.

Abstract: A semiconductor device includes a bit line extending in a first direction on a substrate. A first insulating pattern is disposed on the bit line. A channel pattern is disposed on an upper side of the bit line and a lateral side of the first insulating pattern. The channel pattern includes an oxide semiconductor material. A gate insulating pattern is disposed on the channel pattern. Word lines are disposed on the gate insulating pattern. A second insulating pattern is disposed on the word lines. A landing pad is disposed on the channel pattern. An interlayer insulating layer disposed between the bit line and the channel pattern.