Abstract: An avalanche photodiode with a diffused junction and the method for its fabrication are disclosed. The method comprising forming, on a substrate, a first high-doped region and a low-doped region; performing selective area growth (SAG) with in-situ etchant on the low-doped region to grow a SAG structure; and diffusing through the SAG structure to form a second high-doped region in the low-doped region.

Abstract: A photodetector which comprises a measurement layer (15) and at least a first photoactive layer (11) which covers the measurement layer (15). The measurement layer (15) may be a transistor channel or a charge accumulation electrode. The conductivity type of the measurement layer is n-type, p-type or ambipolar and the first photoactive layer (11) exhibits intrinsic semiconductivity.

Abstract: The present application discloses a display substrate. The display substrate may include a base substrate and a plurality of light emitting structures on the base substrate. Each of the plurality of the light emitting structures includes a first electrode, a light emitting layer, a transparent electrode, an optical adjustment layer and a second electrode, arranged along a direction away from the base substrate. Optical thicknesses of optical adjustment layers in at least two of the plurality of light emitting structures are different.

Abstract: 2D heterostructures comprising Bi2Se3/MoS2, Bi2Se3/MoSe2, Bi2Se3/WS2, Bi2Se3/MoSe2. 2xS2x, or mixtures thereof in which oxygen is intercalated between the layers at selected positions provide high density storage devices, sensors, and display devices. The properties of the 2D heterostructures can be configured utilizing abeam of electromagnetic waves or particles in an oxygen controlled atmosphere.

Abstract: Provided is a memory device including a substrate, a plurality of contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The contacts are respectively disposed on ends of the active areas. The air gaps respectively surround the sidewalls of the contacts.

Abstract: A substrate inspection apparatus includes a light source unit, a pulsed beam matching unit, a substrate support unit, an incidence angle adjusting unit, and a detecting unit. The light source unit emits a first laser beam having a first wavelength and a second laser beam having a second wavelength. The pulsed beam matching unit matches the first laser beam and the second laser beam to superimpose a pulse of the first laser beam on a pulse of the second laser beam in time and space. The substrate support unit supports a substrate to be inspected. The incidence angle adjusting unit adjusts angles of incidence of the matched first laser beam and second laser beams to irradiate the first laser beam and the second laser beam on the substrate, and mixes the first laser beam and the second laser beam to generate an evanescent wave on the substrate. The evanescent wave generates scattered light due to a defect of the substrate.

Abstract: An OLED device comprises a substrate, a first electrode positioned over the substrate, a second electrode positioned over the first electrode, at least one emissive layer positioned between the first and second electrodes in a first region of the OLED device, and a multilayer dielectric reflector stack, comprising a plurality of dielectric reflector layers positioned between the substrate and the first electrode, wherein the multilayer dielectric reflector stack is configured to form an optical cavity with the emissive layer having a Purcell Factor of at least 3.

Abstract: The present relates to a multi-junction photon detector comprising a semiconductor substrate, a plurality of n+ pixels on the top surface and a p+ uniform doping implant on the backside and at least one n-doped layer on the backside, deeper in the substrate bulk than the p+ implant, such that the detector presents a first PN junction corresponding to a drift and signal induction region and comprising the pixels on the substrate, and a second PN junction corresponding to a gain region and comprising the n-doped layer disposed on the backside of the detector active area deeper in the substrate bulk. These two junctions are operated in inverse polarization. The area between them contains a PN junction in direct polarization and it is fully depleted from the free charges.

Abstract: A method for manufacturing a stacked thin film, includes forming a photoelectric conversion layer on a first transparent electrode by sputtering using a target mainly composed of copper in an oxygen containing atmosphere. An oxygen partial pressure of the sputtering is in a range of 0.01 [Pa] or more and 4.8 [Pa] or less, and 0.24×d [Pa] or more and 2.4×d [Pa] or less when a deposition rate is d [?m/min], in formation of the photoelectric conversion layer. A sputtering temperature is 300° C. or more and 600° C. or less, in formation of the photoelectric conversion layer.

Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method includes forming a first etch mask over a stack structure, and removing a portion of the stack structure exposed by the first etch mask. The first etch mask may have a first mask opening with a first lateral dimension. The method may also include forming a second etch mask from the first etch mask. The second etch mask may have a second mask opening with a second lateral dimension that is greater than the first lateral dimension. The method may further include removing another portion of the stack structure exposed by the second etch mask to form the hole structure having a first hole portion and a second hole portion connected to and over the first hole portion.

Abstract: The disclosed technology relates generally to the field of magnetic devices, in particular to magnetic memory devices or logic devices. The disclosed technology presents a magnetic structure for a magnetic device, wherein the magnetic structure comprises a magnetic reference layer (RL); a spacer provided on the magnetic RL, the spacer comprising a first texture breaking layer provided on the magnetic RL, a magnetic bridge layer provided on the first texture breaking layer, and a second texture breaking layer provided on the magnetic bridge layer. Further, the magnetic structure comprising a magnetic pinned layer (PL) or hard layer (HL) provided on the spacer, wherein the magnetic RL and the magnetic PL or HL are magnetically coupled across the spacer through direct exchange interaction.

Abstract: A light extraction apparatus for an organic light-emitting diode (OLED) includes an OLED emitter (100), a plurality of tapered reflectors (210), and a spacer layer (202). Each tapered reflector includes a first surface (212), a second surface (214) opposite to the first surface and comprising a surface area larger than a surface area of the first surface, and at least one side surface (216) extending between the first surface and the second surface. The spacer layer (202) includes a first surface coupled to the OLED emitter and a second surface coupled to the first surface of each of the plurality of tapered reflectors. Light emitted from the OLED passes through the spacer layer and into the plurality of tapered reflectors. The at least one side surface of each of the plurality of tapered reflectors includes a slope to redirect light into an escape cone and out of the second surface of the corresponding tapered reflector.

Abstract: In an embodiment an optoelectronic sensor includes a radiation-emitting semiconductor region, a radiation-detecting semiconductor region, a first polarization filter arranged above the radiation-emitting semiconductor region and including a first polarization direction and a second polarization filter arranged above the radiation-detecting semiconductor region and including a second polarization direction, wherein the first polarization direction and the second polarization direction are perpendicular to each other, wherein a radiation-reflecting or radiation-absorbing layer is arranged on side flanks of the radiation-emitting semiconductor region and/or the radiation-detecting semiconductor region and/or the first polarization filter and/or the second polarization filter.

Abstract: The present disclosure provides a semiconductor structure for reducing capacitive coupling between adjacent conductive features. The semiconductor structure includes a base layer, a plurality of conductive lines, a plurality of dielectric pillars, and a sealing layer having a plurality of sealing caps. The conductive lines are disposed on the base layer. The dielectric pillars are disposed on the base layer and separated from the conductive layer. The sealing caps are disposed between the conductive lines and the dielectric pillars, wherein the sealing caps are in contact with the conductive lines and the dielectric pillars, and separated from the base layer.

Abstract: A substrate, a first n-type contact layer, a buffer layer, a multiplication layer, an electric field control layer, an absorption layer, and a p-type contact layer are provided. An electrically conductive layer is formed in a central portion of the buffer layer. The substrate is made of a semiconductor having thermal conductivity higher than that of InP, such as SiC, and the first n-type contact layer is made of the same semiconductor as that of the substrate but having n-type conductivity. An n electrode is formed over the first n-type contact layer via a second n-type contact layer.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: A method for manufacturing a semiconductor device having a junction field effect transistor, includes: preparing a substrate having a first conductivity type drift layer; forming a first conductivity type channel layer above the drift layer by an epitaxial growth, to thereby produce a semiconductor substrate; forming a second conductivity type gate layer within the channel layer by performing an ion-implantation; forming a second conductivity type body layer at a position separated from the gate layer within the channel layer by performing an ion-implantation; and forming a second conductivity type shield layer at a position that is to be located between the gate layer and the drift layer within the channel layer by performing an ion-implantation. The shield layer is formed to face the gate layer while being separated from the gate layer, and is kept to a potential different from that of the gate layer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.

Abstract: An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack. The method further includes etching the portion of the semiconductor fin to extend the opening into the semiconductor fin. A material of the semiconductor fin encircles the opening in a top-down view of the semiconductor fin. The method further includes epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.

Abstract: Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.