Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution, and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.

Abstract: A method for manufacturing a photoelectric converter includes a first step of preparing a semiconductor substrate including a metal oxide semiconductor (MOS) transistor, a second step of forming a plurality of interlayer insulating films above the semiconductor substrate, and a third step of forming a photoelectric conversion portion above the semiconductor substrate. The second step includes a step of forming a first film containing hydrogen. The third step includes a step of forming a first electrode, a step of forming a photoelectric conversion film, and a step of forming a second electrode. The method includes a step of performing heat treatment between the step of forming the first film and the step of forming the photoelectric conversion film.

Abstract: An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack. The method further includes etching the portion of the semiconductor fin to extend the opening into the semiconductor fin. A material of the semiconductor fin encircles the opening in a top-down view of the semiconductor fin. The method further includes epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: In manufacturing a crystalline silicon-based solar cell, a first intrinsic thin-film is formed on a conductive single-crystalline silicon substrate, and then a hydrogen plasma etching is performed. A second intrinsic thin-film is formed on the first intrinsic thin-film after the hydrogen plasma etching, and a conductive silicon-based thin-film is formed on the second intrinsic thin-film. The second intrinsic thin-film is formed by plasma-enhanced CVD with a silicon-containing gas and hydrogen being introduced into a CVD chamber. The amount of the hydrogen introduced into the CVD chamber during formation of the second intrinsic thin-film is 50 to 500 times an introduction amount of the silicon-containing gas.

Abstract: The disclosure provides a manufacturing method for a thin film transistor, wherein a manufacturing method for a data line and a source/drain specifically includes: S21: respectively manufacturing a data line material film layer and a source/drain material film layer; S22: manufacturing a photoresist material film layer; S23: performing a half-tone method to etch the photoresist material film layer, forming a photoresist layer, and obtaining a first etching substrate; S24: performing a 4-mask process to etch the first substrate, forming the data line on a gate insulating layer, forming the source and the drain on an active layer, and forming a the back channel between the source and the drain to obtain the thin film transistor. The disclosure further provides a manufacturing method for an array substrate, wherein the manufacturing method for an array substrate includes the above-mentioned manufacturing method for a thin film transistor.

Abstract: A measuring device includes two sensor chips that measure a flow rate of a fluid flowing through a pipe, electrode pads extending from a temperature measuring section and from a heater, respectively, toward peripheries of the two sensor chips, and wires that are electrically connected to the electrode pads and via which a measurement signal that is output from the temperature measuring section or the heater is transmitted to outside of the sensor chips. Each of the electrode pads includes a straight portion that extends linearly from the temperature measuring section or the heater and a wide portion that is formed at a leading end of each of the electrode pads and is wider than the straight portion, and an entire surface area of the wide portion is set as a wire-bonding-allowed region, to which one of the wires is to be bonded.

Abstract: A semiconductor device includes a p-type semiconductor substrate; an n-type drift layer on the substrate; an n-type drain region in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer; a p-type gate region on the substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern; n-type source regions in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and n-type surge-current guiding-regions in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

Abstract: In manufacturing a radio frequency (RF) switch, a heat spreader is provided. A first dielectric is deposited over the heat spreader. A trench is etched in the first dielectric. A heating element is deposited in the trench and over at least a portion of the first dielectric. A thermally conductive and electrically insulating material is deposited over at least the heating element, where the thermally conductive and electrically insulating material is self-aligned with the heating element. A conformability support layer is optionally deposited over the thermally conductive and electrically insulating material and the first dielectric. A phase-change material is deposited over the optional conformability support layer and the underlying thermally conductive and electrically insulating material and the first dielectric.

Abstract: A method of manufacturing an organic semiconductor film, including a step of moving a coating blade surface positioned to face a substrate surface in a first direction parallel to the substrate surface, while in contact with an organic semiconductor solution supplied to a portion between the blade surface and the substrate surface to form the organic semiconductor film in the first direction. The coating blade is disposed to have first and second gaps having different separation gap sizes with the substrate surface in a region where the blade surface and the organic semiconductor solution are in contact. The first gap is positioned on an upstream side of the first direction and the second gap, which is smaller than the first gap, is provided on a downstream side. A second gap size is a minimum distance between the substrate surface and the blade surface and is 40 ?m or less.

Abstract: A method and apparatus for forming a flowable film are described. The method includes providing an oxygen free precursor gas mixture to a processing chamber containing a substrate. The oxygen free precursor gas is activated by exposure to UV radiation in the processing chamber. Molecular fragments resulting from the UV activation are encouraged to deposit on the substrate to form a flowable film on the substrate. The substrate may be cooled to encourage deposition. The film may be hardened by heating and/or by further exposure to UV radiation.

Abstract: Embodiments of methods of forming staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a first dielectric layer is formed on a substrate, and a first photoresist layer is formed on the first dielectric layer. A recess is patterned through the first dielectric layer to the substrate by cycles of trim-etch the first dielectric layer. Dielectric/sacrificial layer pairs are formed on the first dielectric layer and filling in the recess. A second photoresist layer is formed on the dielectric/sacrificial layer pairs. The dielectric/sacrificial layer pairs are patterned by cycles of trim-etch the dielectric/sacrificial layer pairs. A second dielectric layer is formed on the first dielectric layer and covering the patterned dielectric/sacrificial layer pairs.

Abstract: There is disclosed an NMR signal processing method for accurately estimating the intensities of p peaks of interest in an NMR spectrum by the use of a mathematical model that represents a time-domain, free induction decay (FID) signal obtained by an NMR measurement as a sum of q signal components. First, q parameters (each being a combination of a pole and a complex intensity) defining q signal components are estimated for each value of the estimation order q of the mathematical model while varying the value of the estimation order q (S34). At each value of the estimation order q, p parameters are selected from the q parameters in accordance with selection criteria (S42, S46). The selected p parameters are evaluated (S48). An optimal value of the estimation order is determined based on the evaluation values produced at the various values of the estimation order q, and p parameters corresponding to the optimal value of the estimation order is identified.

Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture.

Abstract: An anisotropic conductive film contains conductive particles and spacers. The spacers are arranged at a central part of the film in a width direction. The central part of the film in the width direction represents 20 to 80% of the overall width of the film. The height of the spacers in the thickness direction of the anisotropic conductive film is larger than 5 ?m and less than 75 ?m. Such an anisotropic conductive film has a layered structure having a first insulating adhesion layer and a second insulating adhesion layer, wherein the conductive particles are dispersed in the first insulating adhesion layer, and the spacers are regularly arranged on a surface of the first insulating adhesion layer on a side of the second insulating adhesion layer.

Abstract: An LED array and driver design minimizes space requirements and simplifies assembly, while reducing costs. A printed circuit board with LED driver electronics has a central opening through which the LED array is mounted. In one form the LED array is a chip on board (COB) array, the array being circular and fitting closely within the central opening of the PCB. Four integral leaf springs are formed into the flat PCB, in position to push the LED array down when the PCB and LED array are attached against the heat sink. Two of the springs have electrical contacts that make contact with those of the LED array. With the LED array and driver circuit on the face of a light assembly, the space rear of the driver circuit is free to be open to air flow for cooling.

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

Abstract: A semiconductor structure includes a plurality of sub-array structures separated from each other by a plurality of isolation structures. The semiconductor structure further includes a three-dimensional array of memory cells. The memory cells include a plurality of cell groups disposed in the sub-array structures, respectively. The semiconductor structure further includes a plurality of conductive structures. Each of the conductive structures includes a plurality of conductive columns correspondingly disposed in each of the isolation structures along an extending direction of the isolation structures. The conductive columns penetrate through the each of the isolation structures. Each of the conductive columns has a circular cross section.

Abstract: A light-emitting element includes a stack of a first light-emitting layer emitting fluorescent light and a second light-emitting layer emitting phosphorescent light between a pair of electrodes. The second light-emitting layer includes a first layer in which an exciplex is formed, a second layer in which an exciplex is formed, and a third layer in which an exciplex is formed. The second layer is located over the first layer, and the third layer is located over the second layer. An emission peak wavelength of the second layer is longer than an emission peak wavelength of the first layer and an emission peak wavelength of the third layer.

Abstract: A wiring board includes an insulator layer having a top surface, and a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer. The pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density. At least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region.