Abstract: A method to produce a light-emitting device package includes mounting junctions on pads of a metalized substrate, where the junctions are at least partially electrically insulated from each other, and forming wavelength converters, where each wavelength converter is located over a different junction and separated by a gap from neighboring wavelength converters.

Abstract: An electronic device includes a substrate, a plurality of metal pads, and a plurality of light emitting diodes. The metal pads are disposed on the substrate and form an array. Each of the light emitting diodes is electrically connected to at least two of the metal pads. The metal pads include a plurality of dummy metal pads electrically isolated to the light emitting diodes.

Abstract: A micro-electromechanical device includes a semiconductor substrate, in which a first microstructure and a second microstructure of reference are integrated. The first microstructure and the second microstructure are arranged in the substrate so as to undergo equal strains as a result of thermal expansions of the substrate. Furthermore, the first microstructure is provided with movable parts and fixed parts with respect to the substrate, while the second microstructure has a shape that is substantially symmetrical to the first microstructure but is fixed with respect to the substrate. By subtracting the changes in electrical characteristics of the second microstructure from those of the first, variations in electrical characteristics of the first microstructure caused by changes in thermal expansion or contraction can be compensated for.

Abstract: In manufacturing a radio frequency (RF) switch, a heat spreader is provided. A first dielectric is deposited over the heat spreader. A trench is etched in the first dielectric. A heating element is deposited in the trench and over at least a portion of the first dielectric. A thermally conductive and electrically insulating material is deposited over at least the heating element, where the thermally conductive and electrically insulating material is self-aligned with the heating element. A conformability support layer is optionally deposited over the thermally conductive and electrically insulating material and the first dielectric. A phase-change material is deposited over the optional conformability support layer and the underlying thermally conductive and electrically insulating material and the first dielectric.

Abstract: A semiconductor manufacturing device including: a polishing head that is capable of retaining a semiconductor substrate; a polishing pad having a processing surface to be abutted to the semiconductor substrate retained by the polishing head, the processing surface including a groove; a platen that is capable of rotating about a rotary shaft running along a direction intersecting the processing surface, in a state in which the polishing pad is retained by the platen; a measuring section that is configured to output a measurement value indicating a height of the processing surface at a predetermined location along a circumference of a circle centered about the rotary shaft of the platen; and a derivation section that is configured to derive a depth of the groove from the measurement value of the measuring section.

Abstract: One or more embodiments include a display apparatus including an opening, an apparatus for manufacturing the display apparatus, and a method of manufacturing the display apparatus capable of reducing generation of gas or foreign matter.

Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.

Abstract: A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.

Abstract: Solar cell devices as well as method and apparatus for producing solar cell devices are disclosed. Aspects of the disclosure provide a solar cell device that includes a string of solar cells. The string of solar cells are conductively connected in series and arranged in a shingled manner with sides of adjacent solar cells being overlapped. A first metal ribbon segment is conductively bonded to a front surface of an end cell, the front surface being configured to face a light incoming direction to receive energy from a light source.

Abstract: Provided is a memory device including a substrate, a plurality of contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The contacts are respectively disposed on ends of the active areas. The air gaps respectively surround the sidewalls of the contacts.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Abstract: A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts.

Abstract: A rapid testing read out integrated circuit (ROIC) includes phase-change material (PCM) radio frequency (RF) switches residing on an application specific integrated circuit (ASIC). Each PCM RF switch includes a PCM and a heating element transverse to the PCM. The ASIC is configured to provide amorphizing and crystallizing electrical pulses to a selected PCM RF switch. The ASIC is also configured to determine if the selected PCM RF switch is in an OFF state or in an ON state. In one implementation, a testing method using the ASIC is disclosed.

Abstract: A radio frequency (RF) switch includes a heating element, thermally conductive and electrically insulating layer over the heating element, a wetting dielectric layer over the thermally conductive and electrically insulating layer, and a phase-change material (PCM) over the wetting dielectric layer. At least one cladding dielectric layer can be situated over sides and/or over a top surface of the PCM. Each of the wetting dielectric layer, phase change material, and cladding dielectric layer can comprise at least germanium. A transitional dielectric layer can be situated between the thermally conductive and electrically insulating layer and the wetting dielectric layer. A contact uniformity support layer can be situated over the cladding dielectric layer.

Abstract: A display device includes a substrate; an active pattern disposed on the substrate; a first insulating layer; a first conductive layer disposed on the first insulating layer and having a driving gate electrode; a second insulating layer; a second conductive layer disposed on the second insulating layer and having a first storage electrode; a third insulating layer; a third conductive layer disposed on the third insulating layer and having a second storage electrode; and a light-emitting element disposed on the third conductive layer, wherein the second storage electrode overlaps the first storage electrode via the third insulating layer to form a first capacitor, the first storage electrode overlaps the driving gate electrode via the second insulating layer to form a second capacitor, and the driving gate electrode, the first storage electrode, and the second storage electrode at least partially overlap each other.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: A method for forming a cavity in a silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate, and situation of an etching mask on the surface of the silicon substrate. The etching mask has a retarding structure that protrudes into the mask opening, and a first etching projection region. All further edges of the mask opening outside the first etching projection region are situated essentially parallel to {111} planes of the silicon substrate. The method includes an anisotropic etching of the silicon substrate during a defined etching duration. An etching rate in the <111> directions of the silicon substrate is lower than in other spatial directions, and the first retarding structure is undercut in a first undercut direction going out from the first etching projection region.

Abstract: The present disclosure provides a method for manufacturing a conductive line. The method includes steps of providing a substrate; forming a metal layer on the substrate; patterning the metal layer by etching a portion of the metal layer; and performing a post-treatment process on the patterned metal layer in a chamber by injecting a CxHyFz gas and water vapor into the chamber, such that the patterned metal layer avoids from being corroded after the post-treatment process is performed.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A display apparatus including a display substrate, a light-emitting device on the display substrate, an encapsulation substrate on the light-emitting device and bonded to the display substrate, and a diffraction-grating layer on a top surface of the encapsulation substrate, wherein the diffraction-grating layer includes a plurality of diffraction patterns spaced apart from one another by a predetermined distance, and each of the plurality of diffraction patterns has a stacked structure of a lower layer and an upper layer, wherein the lower and upper layers include different materials.